(19)
(11) EP 0 730 293 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
05.11.1997 Bulletin 1997/45

(43) Date of publication A2:
04.09.1996 Bulletin 1996/36

(21) Application number: 96102457.7

(22) Date of filing: 19.02.1996
(51) International Patent Classification (IPC)6: H01L 21/336, H01L 29/10
(84) Designated Contracting States:
DE FR GB IT

(30) Priority: 28.02.1995 US 395339

(71) Applicant: MOTOROLA, INC.
Schaumburg, IL 60196 (US)

(72) Inventors:
  • Chang, Ko-Min
    Austin, Texas 78758 (US)
  • Orlowski, Marius
    Austin, Texas 78739 (US)
  • Swift, Craig
    Austin, Texas 78749 (US)
  • Sun, Shih-wei
    Austin, Texas 78733 (US)
  • Luo, Shiang-Chyong
    Austin, Texas 78759 (US)

(74) Representative: Hudson, Peter David et al
Motorola European Intellectual Property Midpoint Alencon Link
Basingstoke, Hampshire RG21 7PL
Basingstoke, Hampshire RG21 7PL (GB)

   


(54) Process for fabricating a graded-channel MOS device


(57) A process for fabricating a graded-channel MOS device includes the formation of a masking layer (16) on the surface of a semiconductor substrate (10) and separated from the surface by a gate oxide layer (12). A first doped region (22) is formed in a channel region (20) of the semiconductor substrate (10) using the masking layer (16) as a doping mask. A second doped region (24) is formed in the channel region (20) and extends from the principal surface (14) of the semiconductor substrate (10) to the first doped region (22). A gate electrode (34) is formed within an opening (18) in the masking layer (16) and aligned to the channel region (20). Upon removal of the masking layer (16) source and drain regions (36, 38) are formed in the semiconductor substrate (10) and aligned to the gate electrode (34).






Search report