MOS field effect transistor with improved pocket regions and method for fabricating the same

(19)

(11)

EP 0 756 317 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	14.01.1998 Bulletin 1998/03

(43)	Date of publication A2:
	29.01.1997 Bulletin 1997/05

(21)	Application number: 96112232.2

(22)	Date of filing: 29.07.1996

(51)	International Patent Classification (IPC)⁶: H01L 21/336, H01L 21/265, H01L 29/78, H01L 29/10

(84)	Designated Contracting States:
	DE FR GB

(30)

Priority:

28.07.1995 JP 193347/95

(71)	Applicant: NEC CORPORATION
	Tokyo (JP)

(72)	Inventor:
	Masuoka, Sadaaki, c/o NEC Corp. Minato-ku, Tokyo (JP)

(74)	Representative: Baronetzky, Klaus, Dipl.-Ing.
	Patentanwälte Dipl.-Ing. R. Splanemann, Dr. B. Reitzner, Dipl.-Ing. K. Baronetzky Tal 13 80331 München 80331 München (DE)

(54)	MOS field effect transistor with improved pocket regions and method for fabricating the same

(57) There is provided a method for ion-implantation of an impurity of a first conductivity into a substrate (1) of the same conductivity type as the first conductivity to form pocket regions (11) at limited positions in the vicinity of an inside edge portion of source/drain regions (7) of a second conductivity type in a MOS field effect transistor having a gate electrode (4) with side wall silicon oxide films (5). The method comprises the following steps. Semiconductor epitaxial layers (8) are formed on the source/drain regions (7) under conditions of a high selectivity to silicon oxide of the side wall silicon oxide films (5) so that the semiconductor epitaxial layers (8) have facets (9) which face to the side wall silicon oxide films (5) and the facets (9) are almost linearly sloped down to bottom portions of the side wall silicon oxide films (5). The impurity of the first conductivity type is implanted into the substrate (1) at its limited positions in the vicinity of the inside edge portion of the source/drain regions (7) by using the semiconductor epitaxial layers (8) with the facets (9) and the side wall silicon oxide films (5) as masks in an oblique direction tilted by a tilting angle θ from the normal of a surface of the substrate (1), wherein the angle θ satisfies an equation represented by θ ≦ θ₁ where : θ₁ is an angle by which the facets (9) are tilted from the normal of the surface of the substrate (1), and also wherein a thickness of the semiconductor epitaxial layers (8) satisfies an equation represented by Tepi > (Xj' / tan θ) - Xj where : Tepi is the thickness of the semiconductor epitaxial layers (8) except for the facet portions ; Xj is a junction depth of the source/drain diffusion regions ; and Xj' is a distance between a top edge portion of each of the source/drain diffusion regions and a bottom side edge of each of the side wall silicon oxide films (5).

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