(19)
(11) EP 0 757 347 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
10.12.1997 Bulletin 1997/50

(43) Date of publication A2:
05.02.1997 Bulletin 1997/06

(21) Application number: 96305730.2

(22) Date of filing: 02.08.1996
(51) International Patent Classification (IPC)6G11B 20/14, H03M 5/14
(84) Designated Contracting States:
DE FR GB NL

(30) Priority: 03.08.1995 KR 9523993

(71) Applicant: Samsung Electronics Co., Ltd.
Suwon-City, Kyungki-do 441-742 (KR)

(72) Inventors:
  • Ko, Jung-wan
    Suwon-city, Kyungki-do (KR)
  • Chang, Yong-deok
    Suwon-city, Kyungki-do (KR)

(74) Representative: Chugg, David John 
Appleyard Lees, 15 Clare Road
Halifax, West Yorkshire HX1 2HY
Halifax, West Yorkshire HX1 2HY (GB)

   


(54) Control signal generation apparatus for a digital information signal recording system


(57) A control signal generation apparatus for use in a digital information signal recording system enables an optimum channel word of two channel words output from two precoders to be recorded on a digital record medium. The control signal generation apparatus compares (381 - 383) the same kind of components between peak, notch, and dip components detected from the two channel words, and generates a control signal for selecting an optimum channel word. Also, the apparatus comprises a gain controller (400) for controlling gains with respect to integrators used for detecting the peak, notch, and dip components. The gain controller (400) compares the detected peak, notch, and dip components with the upper limit and lower limit reference set values, and generates a gain control signal according to the comparison results. Accordingly, the present invention can reduce the amount of the hardware circuitry, compared with the conventional apparatus which adds the peak, notch, and dip components detected from an individual channel word, and then compares the addition results with each other. Also, using of an automatic gain controller allows the number of the maximum allowable bits to be reduced, and an operational processing speed of an integrator to be increased.







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