(19)
(11) EP 0 771 442 A1

(12)

(43) Date of publication:
07.05.1997 Bulletin 1997/19

(21) Application number: 96913319.0

(22) Date of filing: 01.05.1996
(51) International Patent Classification (IPC): 
G06F 9/ 38( . )
(86) International application number:
PCT/US1996/006146
(87) International publication number:
WO 1996/035165 (07.11.1996 Gazette 1996/49)
(84) Designated Contracting States:
DE FR GB

(30) Priority: 06.05.1995 US 19950445564

(71) Applicant: NATIONAL SEMICONDUCTOR CORPORATION
Santa Clara, CA 95051 (US)

(72) Inventors:
  • DIVIVIER, Robert
    San Jose, CA 95120 (US)
  • NEMIROVSKY, Mario
    San Jose, CA 95129 (US)

(74) Representative: Horton, Andrew Robert Grant, et al 
BOWLES HORTON Felden House Dower Mews High Street
Berkhamsted Hertfordshire HP4 2BL
Berkhamsted Hertfordshire HP4 2BL (GB)

   


(54) INSTRUCTION MEMORY LIMIT CHECK IN MICROPROCESSOR