A PIPELINED MICROPROCESSOR THAT MAKES MEMORY REQUESTS TO A CACHE MEMORY AND AN EXTERNAL MEMORY CONTROLLER DURING THE SAME CLOCK CYCLE - Patent 0772829

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EP 0 772 829 A1

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(43)	Date of publication:
	14.05.1997 Bulletin 1997/20

(21)	Application number: 96920253.0

(22)	Date of filing: 16.05.1996

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International Patent Classification (IPC):

G06F 12/ 08^{( . )}

(86)	International application number:
	PCT/US1996/007091

(87)	International publication number:
	WO 1996/037844 (28.11.1996 Gazette 1996/52)

(84)	Designated Contracting States:
	DE FR GB

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Priority:

26.05.1995 US 19950452306

(71)	Applicant: NATIONAL SEMICONDUCTOR CORPORATION
	Santa Clara, CA 95051 (US)

(72)	Inventors:
	DIVIVIER, Robert San Jose, CA 95120 (US) NEMIROVSKY, Mario, D. San Jose, CA 95129 (US) BIGNELL, Robert San Jose, CA 95127 (US)

(74)	Representative: Horton, Andrew Robert Grant, et al
	BOWLES HORTON Felden House Dower Mews High Street Berkhamsted Hertfordshire HP4 2BL Berkhamsted Hertfordshire HP4 2BL (GB)

(54)	A PIPELINED MICROPROCESSOR THAT MAKES MEMORY REQUESTS TO A CACHE MEMORY AND AN EXTERNAL MEMORY CONTROLLER DURING THE SAME CLOCK CYCLE