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(11) | EP 0 776 012 A3 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | Data read circuit of nonvolatile semiconductor memory device |
| (57) A nonvolatile semiconductor memory device is described including a memory cell array
having a plurality of NAND cell strings, each including a plurality of memory transistors
M1-Mn, and a plurality of bit lines BL1-BL3, one for each NAND cell string. A read
unit for each bit line comprises a switch unit S1 for connecting the NAND cell string
to a first portion of the bit line in response to a selection signal SSL. A precharge
unit P1 precharges a second portion of the bit line in response to a precharge signal
Pbpre. A bias setting transistor N1 discharges the precharge on the second portion
of the bit line to the first portion of the bit line if the voltage level on the first
portion of the bit line is below a given level. A column selecting unit 450 connects
the second portion of the bit line to a common sensing node C in response to a respective
column decoding signal and a sense amplifier 600 senses the voltage on the sensing
node. |