(19)
(11) EP 0 781 012 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
11.10.2000 Bulletin 2000/41

(43) Date of publication A2:
25.06.1997 Bulletin 1997/26

(21) Application number: 96309261.4

(22) Date of filing: 19.12.1996
(51) International Patent Classification (IPC)7: H04L 27/22
(84) Designated Contracting States:
DE FR GB

(30) Priority: 20.12.1995 JP 33143495

(71) Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Kadoma-shi, Osaka-fu (JP)

(72) Inventor:
  • Suzuki, Hidetoshi
    Yokohama-shi (JP)

(74) Representative: Smith, Norman Ian et al
fJ CLEVELAND 40-43 Chancery Lane
London WC2A 1JQ
London WC2A 1JQ (GB)

   


(54) Arithmetic unit


(57) An arithmetic unit performes a demodulating operation (22) for a received signal, a synchronizing operation (23) based on a demodulated signal, a voice decoding operation (24) for the demodulated signal, a voice encoding operation (27) for a voice, and a modulating operation (28) for a coded voice by a pipeline processing method. The arithmetic unit has an arithmetic portion for alternately performing a desired one of the demodulating operation, the modulating operation and the synchronizing operation and a desired one of the voice decoding operation and the voice encoding operation. The arithmetic unit further has a first storage portion for storing a result of the desired one of the demodulating operation, the modulating operation and the synchronizing operation performed by the arithmetic portion; and a second storage portion for storing a result of the desired one of the voice decoding operation and the voice encoding operation performed by the arithmetic portion.






Search report