(19)
(11) EP 0 803 859 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
04.03.1998 Bulletin 1998/10

(43) Date of publication A2:
29.10.1997 Bulletin 1997/44

(21) Application number: 96118476.9

(22) Date of filing: 18.11.1996
(51) International Patent Classification (IPC)6: G09G 5/36
(84) Designated Contracting States:
DE FR GB

(30) Priority: 23.04.1996 US 636250

(71) Applicant: Hewlett-Packard Company
Palo Alto, California 94304 (US)

(72) Inventors:
  • Dykstal, John A.
    Fort Collins, CO 80526 (US)
  • Emmot, Darel N.
    Fort Collins, CO 80526 (US)

(74) Representative: Schoppe, Fritz, Dipl.-Ing. 
Patentanwalt, P.O. Box 71 08 67
81458 München
81458 München (DE)

   


(54) System and method for optimizing storage requirements for an N-way distribution channel


(57) In a texture mapping computer graphics system including a texture mapping chip (46) that stores a plurality of texels (S, T) and multiple frame buffer controller chips (50A-50E) that process the texels, an interface is provided between the texture mapping chip (46) and the frame buffer controller chip. The interface includes a texel array storage unit, coupled between the texture mapping chip (46) and the frame buffer controller chips (50A-50E), that temporarily stores a limited number of texels, each texel being destined for a particular frame buffer controller chip. A control unit (110), coupled to the texel array storage unit (90), controls shifting texels from the texture mapping chip (46) into locations within the texel array storage unit (90) and transferring texels from the texel array storage unit (90) into appropriate frame buffer controller chips (50A-50E). A plurality of address storage units (114A-114E), coupled to the control unit (90), store addresses of locations within the texel array storage unit (90) in which texels are stored. Each address storage unit (114A-114E) corresponds to a different frame buffer controller chip (50A-50E).






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