(57) A differential amplifier circuit having an improved transconductance linearity, which includes a first to fourth unbalanced differential pairs of MOS transistors. In each differential pair, a ratio (W/L) of a gate-width W and a gate-length L of one transistor is different from that of the other transistor. Gates of the transistors having smaller ratios of the first and third pairs and gates of the transistors having larger ratios of the second and fourth pairs are coupled together to form one of differential input ends. Gates of the transistors having larger ratios of the first and third pairs and gates of the transistors having smaller ratios of the second and fourth pairs are coupled together to form the other of the input ends. Drains of the transistors having smaller ratios of the first and second pairs and drains of the transistors having larger ratios of the third and fourth pairs are coupled together to form one of differential output ends. Drains of the transistors having larger ratios of the first and second pairs and drains of the transistors having smaller ratios of the third and fourth pairs are coupled together to form the other of the output ends.