(19)
(11) EP 0 818 879 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
07.04.1999 Bulletin 1999/14

(43) Date of publication A2:
14.01.1998 Bulletin 1998/03

(21) Application number: 97301156.2

(22) Date of filing: 21.02.1997
(51) International Patent Classification (IPC)6: H03G 1/00
(84) Designated Contracting States:
DE FR GB

(30) Priority: 12.07.1996 JP 182915/96

(71) Applicant: FUJITSU LIMITED
Kawasaki-shi, Kanagawa 211 (JP)

(72) Inventors:
  • Kawai, Takahisa
    Nakahara-ku, Kawasaki-shi, Kanagawa 211 (JP)
  • Okamoto, Itsuo
    Nakahara-ku, Kawasaki-shi, Kanagawa 211 (JP)

(74) Representative: Stebbing, Timothy Charles et al
Haseltine Lake & Co., Imperial House, 15-19 Kingsway
London WC2B 6UD
London WC2B 6UD (GB)

   


(54) Amplifier circuit and multistage amplifier circuit


(57) An amplifier circuit includes a first FET of an enhancement type having a gate supplied with an input signal and a gate bias voltage and a drain via which an amplified output signal is output, and a second FET of the enhancement type having a drain connected to a drain voltage source, a source connected to the drain of the first FET, and a gate supplied with a control signal for controlling the drain voltage supplied to the first FET.






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