(19)
(11) EP 0 827 207 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
11.03.1998 Bulletin 1998/11

(43) Date of publication A2:
04.03.1998 Bulletin 1998/10

(21) Application number: 97118479.1

(22) Date of filing: 04.08.1994
(51) International Patent Classification (IPC)6: H01L 27/118, H01L 23/528
(84) Designated Contracting States:
DE FR GB

(30) Priority: 13.08.1993 JP 201566/93

(62) Application number of the earlier application in accordance with Art. 76 EPC:
94305794.3 / 0638936

(71) Applicant: Oki Electric Industry Co., Ltd.
Tokyo (JP)

(72) Inventors:
  • Inoue, Toru, c/o Oki Electric Ind. Co. Ltd.
    Minato-ku, Tokyo (JP)
  • Amiya, Michihiro, c/o Oki Electric Ind. Co. Ltd.
    Minato-ku, Tokyo (JP)
  • Takahashi, Tadao, c/o Oki Electric Ind. Co. Ltd.
    Minato-ku, Tokyo (JP)

(74) Representative: Boydell, John Christopher 
Stevens, Hewlett & Perkins 1 Serjeants' Inn Fleet Street
London EC4Y 1LL
London EC4Y 1LL (GB)

 
Remarks:
This application was filed on 24 - 10 - 1997 as a divisional application to the application mentioned under INID code 62.
 


(54) Gate array LSI


(57) A gate array LSI having functional blocks formed by interconnecting a plurality of basic cells (10) arranged on a semiconductor substrate in matrix form and either signal conductive patterns (7) or first power conductive patterns (5). The first power conductive patterns (5) are disposed on the plurality of basic cells (10) arranged in line and are divided and disposed on the basic cells so that the signal conductive pattern (7) is interposed therebetween. It is therefore possible to improve the efficiency of wiring macrocells.






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