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(11) | EP 0 838 852 A3 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | Integrated circuit with a capacitive structure and method of fabricating the same |
| (57) A capacitive structure on an integrated circuit and a method of making the same are
disclosed, which is particularly useful in random-access memory devices. Generally,
the method of the present invention comprises the steps of forming a substantially
vertical temporary support 54 (preferably by forming a cylindrical aperture in an
insulating layer) on a semiconductor substrate 10 and forming a substantially vertical
dielectric film 32 (preferably a high dielectric constant perovskite-phase dielectric
film, and more preferably barium strontium titanate) on a temporary support 54. The
method further comprises depositing a first conductive (e.g. platinum) electrode 60
on substantially vertical dielectric film 32, and subsequently replacing temporary
support 54 with a second conductive (e.g.platinum) electrode 64, such that a thin
film capacitor 44 which is substantially vertical with respect to substrate 10 is
formed. The entire capacitor is essentially self-aligned, such that some embodiments
require only one lithography step to complete the capacitor. Also, an advantage of
this method is that a high temperature, high oxygen activity dielectric deposition
may be completed prior to formation of either electrode, thus greatly simplifying
both electrode structure and processing. |