(19)
(11) EP 0 844 619 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
09.06.1999 Bulletin 1999/23

(43) Date of publication A2:
27.05.1998 Bulletin 1998/22

(21) Application number: 97120024.1

(22) Date of filing: 14.11.1997
(51) International Patent Classification (IPC)6: G11C 29/00
(84) Designated Contracting States:
AT BE CH DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
Designated Extension States:
AL LT LV RO SI

(30) Priority: 21.11.1996 JP 310785/96

(71) Applicant: NEC CORPORATION
Tokyo (JP)

(72) Inventor:
  • Kobatake, Hiroyuki
    Minato-ku, Tokyo (JP)

(74) Representative: Baronetzky, Klaus, Dipl.-Ing. 
Patentanwälte Dipl.-Ing. R. Splanemann, Dr. B. Reitzner, Dipl.-Ing. K. Baronetzky Tal 13
80331 München
80331 München (DE)

   


(54) Nonvolatile semiconductor memory device having test circuit for testing erasing function thereof


(57) The nonvolatile semiconductor memory of the present invention has erase circuits 30 for supplying predetermined voltage to corresponding blocks, respectively. Each of the erase circuits 30 comprises an erase address detection circuit 33 for detecting whether an erase transistor 31 conducts a switching operation in accordance with a block address signal.






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