<?xml version="1.0" encoding="UTF-8"?><!DOCTYPE ep-patent-document SYSTEM "ep-patent-document-v1-4.dtd">
<ep-patent-document id="EP0851371A3" country="EP" dtd-version="ep-patent-document-v1-4.dtd" doc-number="0851371" date-publ="20021023" file="97122866.3" lang="en" kind="A3" status="n"><SDOBI lang="en"><B000><eptags><B001EP>ATBECHDEDKESFRGBGRITLILUNLSEMCPTIESILTLVFIROMK..AL..............................</B001EP><B005EP>J</B005EP><B007EP>DIM350 (Ver 2.1 Jan 2001)  1620000/0</B007EP></eptags></B000><B100><B110>0851371</B110><B120><B121>EUROPEAN PATENT APPLICATION</B121></B120><B130>A3</B130><B140><date>20021023</date></B140><B190>EP</B190></B100><B200><B210>97122866.3</B210><B220><date>19971224</date></B220><B250>En</B250><B251EP>En</B251EP><B260>En</B260></B200><B300><B310>34504696</B310><B320><date>19961225</date></B320><B330><ctry>JP</ctry></B330></B300><B400><B405><date>20021023</date><bnum>200243</bnum></B405><B430><date>19980701</date><bnum>199827</bnum></B430></B400><B500><B510><B516>7</B516><B511> 7G 06F  17/50   A</B511></B510><B540><B541>de</B541><B542>Verfahren zum Positionieren einer integrierten Schaltung und Vorrichtung zur Durchführung des Verfahrens</B542><B541>en</B541><B542>Method of positioning semiconductor integrated circuit device and apparatus of carrying out the method</B542><B541>fr</B541><B542>Méthode pour positionner un circuit intégré è semi-conducteur et appareil pour la mise en oeuvre de la méthode</B542></B540><B590><B598>6</B598></B590></B500><B700><B710><B711><snm>NEC Corporation</snm><iid>00236697</iid><irf>NI495026EPP00NH</irf><adr><str>7-1, Shiba 5-chome</str><city>Minato-ku, Tokyo 108-8001</city><ctry>JP</ctry></adr></B711></B710><B720><B721><snm>Tajima, Hisayuki, NEC IC Mircocomp. Sys. LTD.</snm><adr><str>403-53, Kosugimachi 1-chome</str><city>Nakahara-ku, Kawasaki-shi, Kanagawa</city><ctry>JP</ctry></adr></B721></B720><B740><B741><snm>von Samson-Himmelstjerna, Friedrich R., Dipl.-Phys.</snm><sfx>et al</sfx><iid>00012469</iid><adr><str>SAMSON &amp; PARTNER Widenmayerstrasse 5</str><city>80538 München</city><ctry>DE</ctry></adr></B741></B740></B700><B800><B840><ctry>AT</ctry><ctry>BE</ctry><ctry>CH</ctry><ctry>DE</ctry><ctry>DK</ctry><ctry>ES</ctry><ctry>FI</ctry><ctry>FR</ctry><ctry>GB</ctry><ctry>GR</ctry><ctry>IE</ctry><ctry>IT</ctry><ctry>LI</ctry><ctry>LU</ctry><ctry>MC</ctry><ctry>NL</ctry><ctry>PT</ctry><ctry>SE</ctry></B840><B844EP><B845EP><ctry>AL</ctry></B845EP><B845EP><ctry>LT</ctry></B845EP><B845EP><ctry>LV</ctry></B845EP><B845EP><ctry>MK</ctry></B845EP><B845EP><ctry>RO</ctry></B845EP><B845EP><ctry>SI</ctry></B845EP></B844EP><B880><date>20021023</date><bnum>200243</bnum></B880></B800></SDOBI><abstract id="abst" lang="en"><p id="p0001" num="0001">There is provided a method of positioning a semiconductor IC device including a plurality of blocks, including the steps of separating data about IC connection into functional blocks (S3), establishing a connection point to each of the functional blocks, establishing an interface pad macro at the connection point for each of the functional blocks, connecting the functional blocks to each other, setting instance names of the interface pad macros to be identical with instance names of the functional blocks, positioning the functional blocks and thereby the interface pad macros, extracting data about positioning of the interface pad macros (S5), inputting the thus extracted data to the functional blocks to thereby position the interface pad macros (S6), and combining the functional blocks with each other (S8). The method makes it possible to arrange and position LSI having different design rules, such as LSI including analog and digital circuits formed on a common substrate.<img id="" file="00000001.TIF" he="112" wi="76" img-content="drawing" img-format="tif" orientation="portrait" inline="no"/></p></abstract><search-report-data id="srep" lang="en" srep-office="EP" date-produced=""><doc-page id="srep0001" file="90000001.TIF" he="231" wi="158" type="tif"/><doc-page id="srep0002" file="90010001.TIF" he="232" wi="159" type="tif"/><doc-page id="srep0003" file="90020001.TIF" he="231" wi="160" type="tif"/></search-report-data></ep-patent-document>
