(19)
(11) EP 0 899 644 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
06.05.1999 Bulletin 1999/18

(43) Date of publication A2:
03.03.1999 Bulletin 1999/09

(21) Application number: 98306464.3

(22) Date of filing: 13.08.1998
(51) International Patent Classification (IPC)6: G05F 3/20
(84) Designated Contracting States:
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
Designated Extension States:
AL LT LV MK RO SI

(30) Priority: 01.09.1997 JP 235652/97

(71) Applicant: ALPS ELECTRIC CO., LTD.
Ota-ku Tokyo 145 (JP)

(72) Inventor:
  • Kanno, Susumu
    Soma-shi, Fukushima-ken (JP)

(74) Representative: Kensett, John Hinton 
Saunders & Dolleymore, 9 Rickmansworth Road
Watford, Hertfordshire WD1 7HE
Watford, Hertfordshire WD1 7HE (GB)

   


(54) Bias voltage stabilizing circuit


(57) Disclosed herein is a bias voltage stabilizing circuit which comprises a dc voltage source, a first voltage drop circuit (10b) having a first diode (11), and a second voltage drop circuit (10c) having a second diode (13). The first voltage drop circuit and the second voltage drop circuit are electrically series-connected to each other and electrically parallel-connected to the dc voltage source. Resistors (12,14) are electrically connected to at least one of the first voltage drop circuit and the second voltage drop circuit in series with either the first diode or the second diode. A closed loop is formed by the dc voltage source, the first diode, the second diode and the resistors. The voltage at a point where the first voltage drop circuit and the second voltage drop circuit are electrically connected to each other, is used as a bias voltage.






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