Semiconductor with lateral insulator

(19)

(11)

EP 0 910 124 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	16.08.2000 Bulletin 2000/33

(43)	Date of publication A2:
	21.04.1999 Bulletin 1999/16

(21)	Application number: 98307577.1

(22)	Date of filing: 17.09.1998

(51)	International Patent Classification (IPC)⁷: H01L 21/762, H01L 21/32

(84)	Designated Contracting States:
	AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
	Designated Extension States:
	AL LT LV MK RO SI

(30)

Priority:

16.10.1997 US 951827

(71)	Applicant: International Business Machines Corporation
	Armonk, N.Y. 10504 (US)

(72)	Inventors:
	Chu, Jack Oon Astoria, New York 11103 (US) Ismail, Khalid EzzEldin Yorktown Heights, New York 10598 (US) Lee, Kim Yang Fremont, California 94538 (US) Ott, John Albrecht Greenwood Lake, New York 10925 (US)

(74)	Representative: Davies, Simon Robert
	IBM, United Kingdom Limited, Intellectual Property Law, Hursley Park Winchester, Hampshire SO21 2JN Winchester, Hampshire SO21 2JN (GB)

(54)	Semiconductor with lateral insulator

(57) A method is provided for forming buried oxide regions 33, 34 below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers 16, 20 having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FETs may be formed. This approach reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FETs and eliminating floating body effects of FET by selectively oxidizing semiconductor layers.

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