Detailed Description of the Invention
Field of the Invention
[0001] The present invention relates to a receiver apparatus for code-division-multiple-access
(CDMA) communication system, particularly to a receiver apparatus having an analog
matched filter for demodulation and a rake combiner for multi-path signal.
Prior Art
[0002] A spread spectrum communication system absorbs attention in the field of mobile communication
and wireless local area network (LAN) due to its high frequency efficiency and its
secrecy.
[0003] In the CDMA communication, the transmission signal is multiplied by a spreading code
and the received signal is despread by the same spreading code at the receiver side.
[0004] A complex matched filter is used for the despread in high speed. A matched filter
of digital circuit is large in circuit size and consumes a lot of electrical power.
The inventors of the resent invention proposed matched filters of high speed and low
power by analog multiplication and addition circuit in the Japanese patent publication
06-164321, 06-164320 and 07-212438.
[0005] A multi-path signal is generated by a reflection on a building etc. of radio wave.
A plurality of correlation peaks occurs within one symbol period when the multipath
signal is despread by the matched filter. A plurality of correlation peaks of higher
levels are selected for each complex component, synchronized and combined. The path
selection and rake combining are performed by a digital circuit, so the complex components,
that is, in-phase ad quadrature components of the output of the analog matched filter
has to be converted by an A/D converter into a digital data. At least a pair of A/D
converters are necessary, which are of higher speed than the chip rate when a over-sampling
is executed. This is disadvantageous for decreasing the electrical power.
Summary of the Invention
[0006] The present invention has an object to provide circuits for multi-path detection
and phase compensation of a small circuit size and low electrical power consumption.
[0007] According to the present invention, an output of a complex matched filter is converted
into a signal of one dimension and the multi-path detection is performed according
to the signal. The analog complex components of the output from the matched filter
is held at its peaks by an analog sampling and holding circuit and is converted into
digital signals.
Brief Description of Drawings
[0008]
Fig.1 is a block diagram of an embodiment of a receiver apparatus for CDMA communication
system according to the present invention,
Fig.2 is a block diagram of a multi-path detection circuit of the embodiment,
Fig.3 is the first variation of the multi-path detection circuit,
Fig.4 is the second variation of the multi-path detection circuit,
Fig.5 is a circuit diagram of an analog-signal-power detection circuit in the multi-path
detection circuit,
Fig.6 is a circuit diagram of an absolute circuit in the analog-signal-power detection
circuit, and
Fig.7 is a circuit diagram of a multi-plexer in the absolute circuit.
Preferred Embodiment of the Present Invention
[0009] Hereinafter, an embodiment of a receiver apparatus for code-division-multiple-access
(CDMA) communication system is described with reference to the attached drawings.
[0010] In Fig.1, a signal Ain1 received by an antenna and a radio frequency (RF) receiver
is output as an intermediate frequency (IF) wave. The IF signal is divided by a quadric
detector into two signals of an in-phase component (I-component or real-component)
and a quadrature-component (Q-component or imaginary-component). These components
are processed by a low-path filters LPF1 and LPF2, respectively, so that carrier component
is removed. Then, the I-component Ri and Q -component Rq are extracted to be input
to a matched filter MF. The matched filter MF receives a short spreading code sequence
SPN or a long spreading code sequence LPN from a spreading code generator PNG so as
to multiply the I- and Q-components by SPN or LPN.
[0011] An output of the matched filter MF is parallelly input to a frame synchronization
circuit FSC, to a multi-path detection circuit MPS and to a phase compensation block
PCB. In FSC, the frame synchronization is detected from a path of the maximal level.
In PCB, a plurality of signals in the output from the matched filter is held at multi-path
timings in response to an output of circuit MPS and the signals are synchronized in
phase.
[0012] An output of the phase compensation circuit PCB is input to a rake combiner RAKE
for rake combining. The rake combiner receives an information on number of signals
in the multi-path signal and on their delay time, so as to perform the rake combining.
The rake combiner RAKE outputs I-compopnet Di and Q-component Dq to a data judgment
circuit DJ for restoring the data transmitted.
[0013] The multi-path detection circuit MPS becomes an "intermittent mode" in response to
an output from the matched filter MF. When the multi-path is detected and determined,
the multi-path detection is unnecessary until the synchronization becomes incomplete
due to some asynchronism of a predetermined level. Then, only the level of the asynchronism
should be observed. This working condition is called the "intermittent mode". The
MPS works once in several symbol periods and sleeps in other time.
[0014] In Fig.2, the multi-path detection circuit MPS includes an analog signal power detection
circuit PWR as an analog signal level detection circuit. The complex components of
the output of the matched filter MF are input to this analog signal power detection
circuit PWR. An output of the analog signal power detection circuit PWR is input to
an A/D converter A/D so as to be converted into a digital signal. After the A/D, there
are serially connected a recursive integration circuit INT and a peak detection circuit
PD. The output of A/D is recurrently integrated. The peak detection circuit PD detects
peaks in an output of the INT of higher level than a predeterminded level.
[0015] The analog signal power detection circuit PWR calculates a signal power

from the components Di and Dq. Since the power is calculated first, only one the
process system is necessary after the PWR. So, the circuit size becomes small and
the power consumption is reduces.
[0016] The recursive integration circuit adds signals of corresponding timing of each symbol
period during a plurality of symbol periods in order to reduce the influence of noise.
The peak detection circuit PD compares the calculated signal power with a predetermined
threshold so as to select one or more paths (multi-path signals). The selection result
is input to a control circuit CTRL in the phase compensation block PCB. The PCB includes
sampling and holding circuit S/H1 and S/H2 for receiving, for each path, the components
Di and Dq, respectively. The sampling nd holding circuits S/H1 and S/H2 are controlled
by the CTRL so as to hold the output of the matched filter only at the timing of peaks.
Outputs of the sampling and holding circuits S/H1 and S/H2 are input to A/D converters
A/D1 and A/D2, respectively, so as to be converted into digital signals. The signals
are detected by a coherent detector SD and input to the rake combiner. Since peak
detection has already completed before the A/D conversion, the process speed of the
A/D conversion, only for peaks, is much slower than a A/D conversion of the total
signal. The process speed is about 10% to several ten % of the full sampling A/D conversion.
When the spreading ratio is 128, the order of over-sampling is two (double-sampling)
and the number of multi-path is four, the A/D conversion speed is decreased to 264/512=52%.
The circuit size and power consumption are decreased.
[0017] Fig.3 shows the second embodiment of the multi-path detection circuit according to
the present invention. As the analog signal level detection circuit, an absolute level
detection circuit ALD is applied in stead of the PWR. The circuit ALD calculates an
addition |
Di|+|
Dq| of the absolute value of components Di and Dq. Then, the calculation can be performed
by a single system similar to the circuit in Fig.2 and the circuits become more simple
than the circuit in Fig.2. However, the calculation accuracy is lower than the circuit
in Fig.2.
[0018] Fig.4 show the third multi-path detection circuit in which the A/D converter at the
input side is omitted. The recursive integration circuit INT and the peak detection
circuit process analog signal as it is. The multi-path detection circuit is simplified
by such construction.
[0019] The analog signal power detection circuit PWR is a circuit for calculating an absolute
value of a complex number. When a real and imaginary components are I and Q, respectively,
the signal power Mag is approximately calculated in good approximation as in the formula
(1).

[0020] Fig.5 shows an embodiment the analog signal power detection circuit PWR of the absolute
value approximation. Absolute value circuit Abs1 and Abs2 are connected to the real
and imaginary components, respectively. Outputs of the circuits Abs1 and Abs2 are
input to a comparator COMP1, and are parallelly input to two one-input-two-outputs
multi-plexers MUX1 and MUX2. The multi-plexers MUX1 and MUX2 alternatively output
one of inputs in response to an output of the comparator COMP1. The multi-plexer MUX1
selects one of the inputs and the multi-plexer MUX2 selects the other of inputs. When
the output of Abs1 is equal to or larger than the output of Abs2, MUX1 selects the
output from Abs1 and MUX2 selects the output from Abs2. While, when the output of
Abs1 is smaller than the output of Abs2, MUX1 selects the output from Abs2 and MUX2
selects the output from Abs1. Outputs of the multi-plexers MUX1 and MUX2 are input
to capacitaces C41 and C42 at their input side, respectively, and the output side
of the capacitances are commonly connected to an input of an inverting amplifier INV4.
A capacitive coupling is constructed by C41 and C42. An output of the inverting amplifier
INV4 is connected through a feedback capacitance C43 back to its input. The capacitance
ratios are as follows:

Therefore, the formula (4) is true when
I ≥
Q and the formula (5) is true when I≤Q.

[0021] As shown in Fig.6, the absolute approximation circuit Abs1 includes a CMOS inverter
I5 for judging whether an input voltage Vin5, corresponding to I in Fig.4, exceeds
a threshold

or not. The CMOS inverter I5 outputs Vdd when Vin5 does not exceed the threshold
and the output is inverted when Vin5 exceeds threshold.
[0022] The input Vin5 is input through a capacitance C51 to an input of an inverter circuit
INV5 an output of which is connected through a feedback capacitance C52 to its input.
Since C51 and C52 have the same capacities, INV5 outputs an inversion of Vin5 with
high accuracy as well as with good stability. Vin5 or its inversion is input to a
multi-plexer MUX5 which is controlled by the output of I5. MUX5 outputs Vin5 when

and outputs the inversion (Vdd-Vin5) when

[0023] The absolute circuit Abs2 is similar to Abs1, so the description therefor is omitted.
[0024] Fig.7 shows the multi-plexer MUX1. MUX1 includes a pair of MOS switches T91 and T92
receiving at their inputs input voltages Vin91 and Vin92, respectively. The MOS switch
T91 has a nMOS receiving a gate control signal C8 and a pMOS receiving an inversion
of C8 generated by an inverter I9. While, the MOS switch T92 has a pMOS receiving
a gate control signal C8 and a nMOS receiving an inversion of C8. The switches T91
and T92 are alternatively closed so as to output Vin91 or Vin92 as an output Vout9.
[0025] The multi-plexer MUX2 and MUX5 are similar to MUX1, so the description therefor are
omitted.
1. A receiver apparatus for CDMA communication system comprising:
an analog complex matched filter for holding successive input signals, for multiplying
complex components of said input signal by PN code sequences, respectively, for summing
said multiplication results of said complex components up and for outputting said
summation result as complex components of output;
a multi-path detection circuit for detecting a predetermined number of multi-path
according to said output of said analog complex matched filter, said multi-path detection
circuit comprising a-1) an analog signal level detection circuit for calculating one
dimensional level from said output a-2) a phase detection circuit for detecting phase
of peaks of said one dimensional levels and for outputting;
a phase compensation circuit comprising a sampling and holding circuit for holding
peaks of said complex components of said output of said analog complex matched filter
in response to said phase detected by said phase detection circuit; and
a rake combiner for rake combining an output of said phase compensation circuit.
2. A receiver apparatus for CDMA communication system as claimed in Claim 1, said a phase
compensation circuit further comprising a pair of A/D converter for converting said
peaks of said components of said output of said analog complex matched filter.
3. A receiver apparatus for CDMA communication system as claimed in Claim 1, wherein
said one dimensional level calculated by said analog signal level detection circuit
is a square root of an addition of second power of said complex components.
4. A receiver apparatus for CDMA communication system as claimed in Claim 1, wherein
said one dimensional level calculated by said analog signal level detection circuit
is an addition of absolute values of said complex components.
5. A receiver apparatus for CDMA communication system as claimed in Claim 2, said multi-path
detection circuit further comprising a recursive integration circuit for adding outputs
from said A/D converter of said phase compensation circuit at corresponding timing
of a plurality of symbol periods and for outputting a result of said addition to said
phase detection circuit, each said symbol period being defined by said multiplication
of each said PN code sequence.
6. A receiver apparatus for CDMA communication system as claimed in Claim 1, said analog
signal level detection circuit comprising;
a first absolute value calculation circuit receiving a first input voltage corresponding
to a real component of said complex component;
a second absolute value calculation circuit receiving a second input voltage corresponding
to an imaginary component of said complex component;
a comparator for outputting alternatively said real or imaginary components in response
to comparison of said components with each other;
a capacitive coupling comprising first and second capacitaces connected at their inputs
to said first and second input voltages, respectively, outputs of said capacitances
being connected with each other for weighting integration of said first and second
input voltages;
an inverting amplifier connected to said outputs of said capacitances of said capacitive
coupling; and
a feedback capacitance connecting output and input of said inverting amplifier.
7. A receiver apparatus for CDMA communication system as claimed in Claim 5, said recursive
integration circuit comprising an analog circuit.
8. A receiver apparatus for CDMA communication system as claimed in Claim 5, said recursive
integration circuit comprising a digital circuit.
9. A receiver apparatus for CDMA communication system as claimed in Claim 1, said multi-path
lex matched filter works intermittently according to said output of said analog complex
matched filter.
10. A receiver apparatus for CDMA communication system as claimed in Claim 9, said analog
complex matched filter works intermittently according to said output of said analog
complex matched filter.