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(11) | EP 0 929 156 A3 |
(12) | EUROPEAN PATENT APPLICATION |
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(54) | Phase locked loop circuit |
(57) Frequencies and phase differences between the oscillation output of a voltage control
oscillation means and a reference signal are compared by a first comparison means,
and a first charging pump charges and discharges a time constant circuit based on
the comparison result performed by the first comparison means. Frequencies and phase
differences between the oscillation output of the voltage control oscillation means
and the reference signal are also compared by a second comparison means having a buffer
amplifying the output of a flip-flop circuit constituting the first comparison circuit,
and a second charging pump charges and discharges the time constant circuit based
on the comparison result performed by the second comparison means. The gain of the
phase difference versus outputting voltage characteristic of the second comparison
means is higher than that of the first comparison means, and the second comparison
means has a dead zone in said phase difference versus outputting voltage characteristic.
On the other hand, a first delaying circuit for resolving a dead zone is inserted
into the first comparison means. |