(19)
(11) EP 0 929 156 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
08.11.2000 Bulletin 2000/45

(43) Date of publication A2:
14.07.1999 Bulletin 1999/28

(21) Application number: 99100076.1

(22) Date of filing: 05.01.1999
(51) International Patent Classification (IPC)7H03L 7/087
(84) Designated Contracting States:
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
Designated Extension States:
AL LT LV MK RO SI

(30) Priority: 06.01.1998 JP 1201598

(71) Applicant: NEC CORPORATION
Tokyo (JP)

(72) Inventor:
  • Kawaguchi, Manabu c/o NEC Corporation
    Tokyo (JP)

(74) Representative: Glawe, Delfs, Moll & Partner 
Patentanwälte Postfach 26 01 62
80058 München
80058 München (DE)

   


(54) Phase locked loop circuit


(57) Frequencies and phase differences between the oscillation output of a voltage control oscillation means and a reference signal are compared by a first comparison means, and a first charging pump charges and discharges a time constant circuit based on the comparison result performed by the first comparison means. Frequencies and phase differences between the oscillation output of the voltage control oscillation means and the reference signal are also compared by a second comparison means having a buffer amplifying the output of a flip-flop circuit constituting the first comparison circuit, and a second charging pump charges and discharges the time constant circuit based on the comparison result performed by the second comparison means. The gain of the phase difference versus outputting voltage characteristic of the second comparison means is higher than that of the first comparison means, and the second comparison means has a dead zone in said phase difference versus outputting voltage characteristic. On the other hand, a first delaying circuit for resolving a dead zone is inserted into the first comparison means.







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