The present invention relates to a high-speed digital accumulator with wide dynamic range. More particularly, the invention relates to a high-speed digital accumulator with wide dynamic range which uses a twos-complement digital adder.

It is known that digital accumulators consist of an adder which receives an input and the value of the accumulator itself in the preceding time period. In practice, the transfer function of said digital accumulators in Z-transforms is as follows:$$\mathit{\text{Y}}\text{=}\frac{\mathit{\text{z}}}{\mathit{\text{z}}\text{-1}}\text{·}\mathit{\text{X}}$$

Figure 1 illustrates a digital accumulator executed according to the prior art.

As shown in Figure 1, the accumulator thus comprises a digital adder 1, the input whereof receives an addend X which is m bits long and also receives the value of the accumulator during the preceding clock period; said value has a length of n bits, since the adder is an n-bit adder. In this case, the output datum Y has a length of n bits.

The reference numeral 2 designates an accumulation register for the result of the adder 1.

In this structure it is assumed that n is much larger than m.

The above-described structure has the drawback that it is inherently slow, since the sum performed by the adder 1 must be completed in a time which is short enough to satisfy the following relation:$${\text{T}}_{\text{sum(n)}}{\text{+T}}_{\text{setup}}{\text{< T}}_{\text{clock}}$$

The pass time of the n-bit adder 1 added to the setup time of the bank of the register 2 must be shorter than the clock time with which the structure is supplied.

Accordingly, it is sometimes difficult to satisfy the above relation, especially in high-speed applications, where it is not possible to use simple ripple-carry adders and therefore structures of the look-ahead or carry select type are used, always with the ultimate goal of satisfying the above equation.

Japanese Patent publication no. JP 62-027864A discloses an accumulator having a first adder stage, in which an input addend is added to a value of a least significant part of an accumulator at a preceding clock period, and at least one second stage, which comprises incrementer/decrementer means for performing an increment or a decrement operation on a most significant part of said accumulator; the accumulation, overflow and up/down count are performed in the same single clock cycle.

The aim of the present invention is therefore to provide a high-speed digital accumulator with wide dynamic range which has a very large number of significant digits with respect to the operating frequency.

Within the scope of this aim, an object of the present invention is to provide a high-speed digital accumulator with wide dynamic range which allows to perform the operation of a digital accumulator in at least two clock cycles by means of a pipeline.

Another object of the present invention is to provide a high-speed digital accumulator with wide dynamic range which uses a high-speed, reduced-area twos-complement digital adder.

Another object of the present invention is to provide a high-speed digital accumulator with wide dynamic range which is highly reliable, relatively easy to manufacture and at competitive costs.

This aim, these objects and others which will become apparent hereinafter are achieved by a high-speed digital accumulator with wide dynamic range according to claims 1 and 9.

Further characteristics and advantages of the invention will become apparent from the description of a preferred embodiment of the digital accumulator according to the invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein:

• Figure 1 is a block diagram of a conventional digital accumulator; and
• Figure 2 is a block diagram of a digital accumulator executed according to the present invention.

Figure 1 was described earlier and therefore is not described further in this part of the description.

Accordingly with reference to Figure 2, the digital accumulator according to the present invention, generally designated by the reference numeral 10, comprises a digital adder 15 which receives in input an m-bit addend X and the output 11 of the adder, i.e., the value of the accumulator at the preceding time period, which is m bits long. A register 16 accumulates the result of the adder 15 and a register 17 accumulates in each instance the m bits in output from the digital adder 15.

The output of the register 17 is therefore again m bits long.

The second stage of the structure of Figure 2 provides for an increment, decrement or identity operation performed in incrementer/decrementer means 18 which receive in input the sign of the addend X, i.e., one bit; the incrementer/decrementer means 18 receive in input the overflow 19 in output from the adder 15, acquired at the preceding time period, and the most significant part of the accumulator y₁ acquired at the preceding period.

The incrementer/decrementer means 18 contain a truth table, on the basis of which a decision is made to perform an increment, a decrement or an identity on the most significant part y₁ of the accumulator. The decision is made on the basis of the results of the preceding stage.

Additional registers 20 and 21 are provided to accumulate respectively the overflow 19 and the sign of the addend X.

Finally, a register 22 is provided in order to accumulate the most significant part y₁ of the accumulator.

The output of the register 22 has a length of n-m bits, which are combined with the m bits in output from the register 17. Accordingly, the output of the accumulator according to the invention has a total length of n bits.

The truth table contained in the incrementer/decrementer means 18 prescribes that if the sign of the addend X is equal to 1 at the preceding time period and the overflow at the same period is equal to 0, then the most significant part y₁ is decremented by 1; if instead the sign of the addend X at the preceding time period is 0 and the overflow 19 at the same period is 1, then the most significant part y₁ is equal to the most significant part y₁ at the preceding period, increased by 1.

If the sign of the addend X at the preceding time period is equal to 1 and the overflow 19 at the same period is 1, then the most significant part y₁ is equal to the most significant part at the preceding period; finally, if the sign of the addend X at the preceding time period is 0 and the overflow 19 calculated at the same period is equal to 0, then the most significant part is equal to the most significant part at the preceding time period.

In this manner, in the first stage of the accumulator according to the invention the input is added to the most significant part of the accumulator, while the second stage merely performs an increment/decrement operation, or neither of these, on the most significant part of the accumulator, on the basis of the outcome of a decision made according to the above-described truth table, in which the results acquired in the preceding stage are entered.

Accordingly, an accumulation with two clock cycles of latency is obtained, but the above-described equation is converted into the following pair of equations, where the addition time, in this case, is equal to the time of the decision made in the incrementer/decrementer means 18 plus the increment/decrement time also provided in the same means 18.$${\text{T}}_{\text{sum(m)}}{\text{+T}}_{\text{setup}}{\text{< T}}_{\text{clock}}$$$${\text{T}}_{\text{decision}}{\text{+T}}_{\text{incdec( n-m)}}{\text{+T}}_{\text{setup}}{\text{< T}}_{\text{clock}}$$

The operation of the accumulator depends only on one of the two preceding equations and particularly on the one that has the biggest first member.

Since m is much smaller than n, it is evident that it becomes possible to considerably increase the clock frequency without sacrificing anything in terms of number of significant digits.

In practice it has been observed that the digital accumulator according to the present invention fully achieves the intended aim and objects, since it allows to provide the transfer function of a digital accumulator in two or more clock cycles by means of a pipeline.

It is possible to extend the above-described structure by increasing the number of stages in the pipeline. In this manner it is possible to increase the bits in the most significant part of the accumulator without thereby having to reduce the clock frequency.

Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the interpretation of each element identified by way of example by such reference signs.