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DIM360 (Ver 1.5 21 Nov 2005) - 2100000/0
0972371
EUROPEAN PATENT SPECIFICATION
B1
20060510
EP
99900091.2
19990118
20000131
20050301
en
en
en
12321
19980123
US
20060510
200619
20000119
200003
20060510
200619
20051004
H04L 7/00 20060101AFI19990816BHEP
de
VERFAHREN ZUR SYNCHRONISIERUNG VON NETZWERKKNOTEN
en
METHOD FOR SYNCHRONIZING NETWORK NODES
fr
PROCEDE PERMETTANT DE SYNCHRONISER LES NOEUDS D'UN RESEAU
EP-A2- 0 253 096
EP-B1- 0 522 607
WO-A1-95/02294
WO-A1-97/04614
US-A- 4 815 110
US-A- 5 525 921
US-A- 5 689 688
SATO, Takashi
Prof. Holstlaan 6
NL-5656 AA Eindhoven
NL
Koninklijke Philips Electronics N.V.
00200769
PHA 23.362 EP
Groenewoudseweg 1
5621 BA Eindhoven
NL
Groenendaal, Antonius W. M.
et al
00059381
Philips Intellectual Property & Standards P.O. Box 220
5600 AE Eindhoven
NL
DE
FR
GB
IB1999000059
19990118
en
WO1999038287
19990729
199930

BACKGROUND OF THE INVENTION
The present invention relates generally to the technology of synchronizing cycle master and cycle slave nodes in one or more networks or sub-networks, and, more particularly, to a technique for synchronizing a cycle master node to a cycle slave node using synchronization information from an external network or sub-network which is supplied to the cycle slave node.
In conventional networks, various electronic components (e.g., computers, consumer electronics devices, appliances, office automation equipment, etc.) are interconnected by a local bus (typically a serial bus, such as the serial bus defined by the IEEE 1394 standard, which is commonly referred to as the "IEEE 1394" bus). Each of the components interconnected by the local bus are referred to as "nodes" on that bus. Typically, one of the nodes on the local bus (commonly referred to as the "local cycle master") serves to generate and distribute a common cycle clock to all other nodes (commonly referred to as "cycle slave nodes") on that bus. In general, each of the cycle slave nodes has a cycle timer which is synchronously updated by the local cycle master.
Some networks consist of a plurality of individual networks (each of which has its own local bus). These individual networks within the overall network are commonly referred to as "sub-networks". The sub-networks are linked or interconnected by one or more "bridges".
Some networks employ network-wide cycle clock ("cycle") synchronization. When the network is subdivided into sub-networks, the local cycle master of each sub-network must be synchronized to the network-wide ("global") cycle master in order to ensure the network-wide clock synchronization. In such networks, each of the local cycle masters are located in one or more of the bridges within the network. Typically, each local cycle master is contained within a "bridge portal".
For example, in a known network having two sub-networks which are interconnected by a bridge having a first bridge portal connected to the local bus of a first one of the two sub-networks, and a second bridge portal connected to the local bus of a second one of the two sub-networks, the local cycle master for the first sub-network is contained in the first bridge portal, and the local cycle master for the second sub-network is contained in the second bridge portal. Network-wide clock synchronization is achieved by passing the clock synchronization information between the local cycle masters (i.e., between the first and second bridge portals). However, it is not always desired or even possible to locate the local cycle masters in the bridges. Thus, what is required is a technology which allows a non-bridge node to be the local cycle master while ensuring the network-wide clock synchronization through one or more bridges within the network. More broadly, what is presently needed in this field is a mechanism to synchronize a cycle master node to one of the cycle slave nodes within a network which includes one or more sub-networks. The present invention fulfills this need.
Document US-A-5.689.688 (International Business Machines Corporation, 18 November 1997) discloses a method for synchronising local times, maintained at nodes within a network architecture, with a reference time. The local time of a node can be synchronised to the reference time by means of a handshaking protocol between the reference time keeper and the local node, or by having the local node eavesdrop broadcast time-messages sent by the reference time keeper.

SUMMARY OF THE INVENTION
The present invention, in one of its aspects, encompasses a method for synchronizing a cycle master node to a cycle slave node, including the steps of utilizing logic circuitry in the cycle slave node to determine a timer offset value, in response to the cycle slave node receiving synchronization information, transmitting the timer offset value to the cycle master node, and,
utilizing logic circuitry in the cycle master node to adjust a value of a cycle master node cycle timer on the basis of the timer offset value. The synchronization information is preferably a cycle reset signal that is asserted at a prescribed rate which is a multiple of one cycle of the cycle slave node cycle timer. In the disclosed embodiment, the cycle slave node further includes a timer offset register, and the cycle master node further includes a timer adjustment register.
The step of utilizing the logic circuitry in the cycle slave node to determine the timer offset value preferably includes the sub-steps of:
- detecting the cycle reset signal;
- reading a value of the cycle slave node cycle timer;
- deriving the timer offset value from the value read out of the cycle
- slave node cycle timer; and,
- loading the timer offset value into the timer offset register.
The step of transmitting the timer offset value to the cycle master node preferably includes the sub-steps of:
- reading the timer offset value from the timer offset register; and,
- sending the timer offset value to the cycle master node using an asynchronous data transfer protocol.
The step of utilizing the logic circuitry in the cycle master node to adjust a value of the cycle master node cycle timer preferably includes the sub-steps of:
- loading the timer offset value received from the cycle slave node into the timer adjustment register;
- reading a value of the cycle master node cycle timer;
- subtracting the timer offset value from the value read out of the cycle master node cycle timer to produce an adjusted cycle timer value;
- deriving a final adjusted cycle timer value from the adjusted cycle timer value; and,
- loading the final adjusted cycle timer value into the cycle master node cycle timer.
The sub-step of deriving the timer offset value from the value read out of the cycle slave node cycle timer preferably includes the sub-steps of:
- calculating a number of clock cycles that have elapsed between a first time at which the cycle reset signal was detected and a second time at which the value was read out of the cycle slave node cycle timer; and,
- subtracting the result of the above calculating step from the value read out of the cycle slave node cycle timer, whereby the result of the subtracting step constitutes the timer offset value.
The sub-step of deriving the final adjusted cycle timer value preferably includes the sub-steps of:
- calculating a number of clock cycles required to perform all required processing starting from a first time at which the value is read out of the cycle master node cycle timer and ending with a second time at which the final adjusted cycle timer value is loaded into the cycle master node cycle timer; and,
- adding the result of the above calculating sub-step to the adjusted cycle timer value, whereby the result of the adding step is the final adjusted cycle timer value.
In a disclosed embodiment, the cycle master node and the cycle slave node are part of a first network or sub-network, and the synchronization information is supplied by a second network or sub-network that is external to the first network or sub-network.
Preferably, the method of the present invention further includes the step of regularly distributing the value of the cycle master node cycle timer to all of the cycle slave nodes in the first network or sub-network, whereby all of the cycle slave nodes in the first network or sub-network are synchronized to the cycle reset signal.
The present invention encompasses, in another of its aspects, a system implementing the method of the present invention. The present invention also encompasses a network which includes:
- a first sub-network which includes a plurality of first nodes connected to a first local bus;
- a second sub-network which includes a plurality of second nodes connected to a second local bus;
- a bridge which interconnects the first and second sub-networks, wherein the bridge includes:
  - a first bridge portal coupled to the first local bus;
  - a second bridge portal coupled to the second local bus; and,
  - an interconnect system which interconnects the first and second bridge portals; and,
wherein a selected one of the first nodes which serves as a local cycle master of the first sub-network is a non-bridge node, and a selected one of the second nodes which serves as a local cycle master of the second sub-network is a non-bridge node.
In a disclosed embodiment, the first and second bridge portals each contain a cycle slave node constructed in accordance with the present invention, and the local cycle masters for the first and second sub-networks each comprise a cycle master node constructed in accordance with the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS
These and other features, objects, and advantages of the present invention will become more clearly understood from the following detailed description read in conjunction with the attached drawings, in which:
- FIG. 1 is a block diagram of a system which implements the method of a preferred embodiment of the present invention;
- FIG. 2 is a block diagram of a network constructed in accordance with an exemplary embodiment of the present invention; and,
- FIG. 3 is a block diagram of a network constructed in accordance with another exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION
With reference now to FIG. 1, there can be seen a block diagram of a system which implements the method of the present invention, which will now be described. More particularly, there can be seen a cycle slave node 20 and a cycle master node 22. The cycle slave node includes a microcontroller 24, a timer offset register 26, and a cycle clock subsystem 27 which includes a cycle timer 30 that is clocked by a crystal 28 which runs at a prescribed clock. The cycle master node 22 includes a microcontroller 32, a timer adjustment register 34, and a cycle clock subsystem 35 which includes a cycle timer 38 that is clocked by a crystal 36 which runs at the prescribed clock rate. Each of the cycle timers 30 and 38 preferably includes separate registers or data fields, including one field for storing a fractional value which indicates the fraction of the current cycle which the current timer value (i.e., current count) represents, and another field for storing a total cycle count which indicates the total (running/cumulative) number of cycles which the cycle timer has gone through.
As in conventional networks, the cycle master node 22 regularly distributes its cycle timer value to all of the other nodes (i.e., all of the cycle slave nodes) in the network or local sub-network which it is a part of, whereby the cycle timers in all of the cycle slave nodes (including the cycle timer 30 in the cycle slave node 20) within that network or sub-network are each synchronized to the cycle timer 38 in the cycle master node 22.
However, in accordance with the present invention, one of the cycle slave nodes in the network or sub-network, shown as the cycle slave node 20 in FIG. 1, receives a synchronous timer reset signal from an external network or sub-network, via reset line 40. This reset signal is regularly asserted at a prescribed rate that is preferably a multiple of one cycle.
A "cycle" as the term is used herein refers to the time period required for a cycle timer to count from an initial value to its final value, whereupon the timer register wraps around and goes back to its initial value. For example, if the cycle timer is implemented as a modulo-N counter, then a "cycle" is the time period required for the counter to count from its initial value (A) to (A) + N-1 before wrapping back around to its initial value (A). The initial value is typically zero (0).
In accordance with the present invention, the microcontroller 24 of the cycle slave node 20 is programmed to perform a control algorithm which includes the following steps:
1. (1) detect the external synchronous cycle reset signal;
2. (2) read the fractional value (less than one cycle) of the cycle timer 30. Preferably, the fractional value is expressed as an integer which is positive if the current cycle timer value (i.e., current count) is less than or equal to N/2, and which is negative if the current cycle timer value is greater than N/2, although this scheme is not limiting to the present invention (e.g., the threshold for positive/negative transition can be set at any suitable value between the initial value and maximum value of the cycle timer 30). For example, assuming the cycle timer 30 has a modulus (N) of 8,000, then the fractional value (I) can be expressed as a positive integer value equal to the current count (X) of the cycle timer 30 if the current count is ≤ 4,000, and can be expressed as a negative integer value equal to the difference between the current count (X) and the modulus (N) of the cycle timer 30 if the current count (X) is > 4,000, i.e., if X ≤ N/2, then I = X, which is a positive integer value, and if X > N/2, then I = (X - N), which is a negative integer value;
3. (3) calculate how many clock cycles have passed between the time that the external synchronous cycle reset signal was detected and the time the fractional cycle timer value was read;
4. (4) subtract the result of step (3) from the fractional cycle timer value read in step (2);
5. (5) load the result of step (4) as a timer offset value in the timer offset register 26; and,
6. (6) read the timer offset value from the timer offset register 26 and send that timer offset value to the cycle master node 22 at a convenient time, e.g., using an asynchronous data transfer mechanism. However, if the timer offset value is zero, it does not need to be sent to the cycle master node 22 (since, in that event, no adjustment of the value of the cycle timer 38 in the cycle master node 22 is necessary).
It should be readily appreciated that steps (3) and (4) can be eliminated if the invention is implemented entirely in hardware (rather than using a programmed microcontroller), or in any other convenient manner which eliminates this processing delay or which results in a fixed processing delay which can be accounted for as such in deriving the timer offset value.
In further accordance with the present invention, the microcontroller 32 of the cycle master node 22 is programmed to perform a control algorithm which includes the following steps:
1. (1) load the timer offset value received from the cycle slave node 20 into the timer adjustment register 34;
2. (2) read the fractional value (less than one cycle) of the cycle timer 38.
3. (3) subtract the timer offset value read out of the timer adjustment register 34 in step (1) from the fractional cycle timer value read out of the cycle timer 38 in step (2);
4. (4) calculate how many clock cycles are required to perform all required processing starting from the time that the fractional cycle timer value is read out of the cycle timer 38 in step (2) and ending with the time that the final (adjusted) cycle timer value is loaded into the cycle timer 38 (i.e., at step (6) below);
5. (5) add the result of step (3) to the result of step (4), and perform any required wrap-around processing of the cycle timer 38. For example, in the event the sum is greater than the maximum value (i.e., in the event an overflow condition has occurred), then the modulus (N) of the cycle timer 38 must be subtracted from the sum to arrive at a resultant value, and the total cycle count must then be incremented by one; and, in the event the sum is less than the initial value (i.e., in the event an underflow condition has occurred), then the modulus (N) of the cycle timer 38 must be added to the sum to arrive at a resultant value, and the total cycle count must then be decremented by one; and,
6. (6) load the resultant value of step (5), which constitutes an adjusted cycle timer value, into the cycle timer 38.
It should be readily appreciated that step (4) can be eliminated if the invention is implemented entirely in hardware (rather than using a programmed microcontroller), or in any other convenient manner which eliminates this processing delay or which results in a fixed processing delay which can be accounted for as such in deriving the timer offset value.
By virtue of the above-described method of the present invention, the cycle timer value of the cycle master node 22 is synchronized to the external synchronous cycle reset signal, thus keeping the cycle timers in all of the cycle slave nodes (including the cycle timer 30 in the cycle slave node 20) within the network or sub-network synchronized to the external synchronous cycle reset signal. It will be appreciated by those skilled in the pertinent art that the method (and system) of the present invention is simple, reliable, and relatively immune to data (e.g., packet) losses or infrequent feedback from the cycle slave node.
With reference now to FIG. 2, there can be seen a network 50 constructed in accordance with an exemplary embodiment of the present invention. The network 50 includes a plurality of nodes Na connected to a local bus A of a sub-network A and a plurality of nodes Nb connected to a local bus B of a sub-network B. The sub-networks A and B are interconnected by a bridge 56 which includes a bridge portal A which is coupled to the local bus A, and a bridge portal B which is coupled to the local bus B. The bridge portals A and B are interconnected by a wired or wireless interconnect system (sometimes referred to as an "internal fabric") 55.
The bridge portal A contains a cycle slave node 60 constructed in accordance with the present invention (e.g., like the cycle slave node 20 depicted in FIG. 1), and the bridge portal B contains a cycle slave node 62 constructed in accordance with the present invention (e.g., like the cycle slave node 20 depicted in FIG. 1).
The local cycle master for the sub-network A (which is like the cycle master node 22 depicted in FIG. 1) can advantageously be any selected one of the nodes Na connected to the local bus A of the sub-network A, and the local cycle master for the sub-network B (which is like the cycle master node 22 depicted in FIG. 1) can advantageously be any selected one of the nodes Nb connected to the local bus B of the sub-network B.
Thus, with this exemplary embodiment, all of the nodes Na of the sub-network A, except for the one designated to be the local cycle master, are suitably implemented as conventional slave nodes, and all of the nodes Nb of the sub-network B, except for the one designated to be the local cycle master, are also suitably implemented as conventional slave nodes. Thus, each of the local cycle masters is a non-bridge node. Of course, it will be readily apparent that, alternatively, either one of the bridge portals A or B can contain the cycle master node, rather than the cycle slave node, in which case, only one of the local cycle masters is a non-bridge node.
With reference now to FIG. 3, there can be seen a network constructed in accordance with another exemplary embodiment of the present invention. The network includes a plurality of local buses, including local buses A, B, and C, and a plurality of bridges, including bridges A and B. It will be readily appreciated that the number of bridges and buses in the network that can be daisy-chained together is virtually unlimited.
With the presently available technology, a fixed one of the two bridges A or B must contain the local cycle master for local bus A. However, with the present invention, it is possible for either selected one of the two bridges A or B to contain a cycle master node constructed in accordance with the present invention, and for the other one of the two bridges B or A to contain the cycle slave node constructed in accordance with the present invention. Thus, the network designer is afforded much greater flexibility in configuring or reconfiguring the network, since he/she is not locked into a fixed one of the bridges A or B having to contain the local cycle master for the local bus A.
Although the present invention has been described in detail hereinabove, it should be clearly understood that many variations and/or modifications of the basic inventive concepts taught herein which may appear to those skilled in the pertinent art will still fall within the scope of the present invention as defined in the appended claims.
For example, although the control algorithms described hereinabove are executed by suitably-programmed microcontrollers 24 and 32, it will be readily apparent to those skilled in the pertinent art that any convenient hard-wired or programmable digital signal processing or logic circuitry could be alternatively utilized.
Further, although the timer offset register 26 and the timer adjustment register 34 have been described as separate registers, it will be readily apparent that they can be implemented as a single register in terms of addressing, if the invention is implemented in hardware, since in that case, the timer offset register 26 can be read-only, while the timer adjustment register 34 can be write-only.
The registers and logic circuitry employed to implement the method of the present invention can be implemented in software using existing link-layer chips (e.g., an IEEE 1394 link-layer chip), and can advantageously be implemented in hardware in future link-layer chips currently under development.
It should also be appreciated that every node (or selected nodes) within a given network can be manufactured to have the capability to serve as either a cycle master node or a cycle slave node in accordance with the present invention, e.g., by simply incorporating therein all of the necessary hardware and/or software, including both the timer offset register 26 and the timer adjustment register 34 (or equivalents thereof).
1. A method for synchronizing a cycle master node (22) to a cycle slave node (20) in a network wherein a cycle timer (30) in the cycle slave node is synchronized to a cycle timer (38) in the cycle master node, including the steps of:
utilizing logic circuitry (24) in the cycle slave node (20) to determine a timer offset value, in response to the cycle slave node (20) receiving synchronization information from an external network or sub-network;
transmitting the timer offset value to the cycle master node (22); and,
utilizing logic circuitry (32) in the cycle master node (22) to adjust a value of the cycle master node cycle timer (38) on the basis of the timer offset value.
2. The method as set forth in Claim 1, wherein the synchronization information includes a cycle timer reset signal.
3. The method as set forth in Claim 2, wherein:
the cycle timer (30) in the cycle slave node (20) counts from an initial value to a final value during a cycle; and,
the cycle timer reset signal is asserted at a prescribed rate which is a multiple of one cycle of the cycle slave node cycle timer (30).
4. The method as set forth in Claim 3, wherein:
the cycle slave node (20) further includes a timer offset register (26);
the cycle master node (22) further includes a timer adjustment register (34);
the step of utilizing the logic circuitry (24) in the cycle slave node (20) to determine the timer offset value includes the sub-steps of:
detecting the cycle timer reset signal;
reading a value of the cycle slave node cycle timer (30);
deriving the timer offset value from the value read out of the cycle;
slave node cycle timer (30); and,
loading the timer offset value into the timer offset register (26).
5. The method as set forth in Claim 4, wherein the step of transmitting the timer offset value to the cycle master node (22) includes the sub-steps of:
reading the timer offset value from the timer offset register (26); and,
sending the timer offset value to the cycle master node (22) using an asynchronous data transfer protocol.
6. The method as set forth in Claim 4, wherein the step of utilizing the logic circuitry (32) in the cycle master node (22) to adjust a value of the cycle master node cycle timer (38) includes the sub-steps of:
loading the timer offset value received from the cycle slave node (20) into the timer adjustment register (34);
reading a value of the cycle master node cycle timer (38);
subtracting the timer offset value from the value read out of the cycle master node cycle timer (38) to produce an adjusted cycle timer value;
deriving a final adjusted cycle timer value from the adjusted cycle timer value; and,
loading the final adjusted cycle timer value into the cycle master node cycle timer (3 8).
7. The method as set forth in Claim 4, wherein the sub-step of deriving the timer offset value from the value read out of the cycle slave node cycle timer (30) includes the sub-steps of:
calculating a number of clock cycles that have elapsed between a first time at which the cycle timer reset signal was detected and a second time at which the value was read out of the cycle slave node cycle timer (30); and,
subtracting the result of the above calculating step from the value read out of the cycle slave node cycle timer (30), whereby the result of the subtracting step constitutes the timer offset value.
8. The method as set forth in Claim 6, wherein the sub-step of deriving the final adjusted cycle timer value includes the sub-steps of:
calculating a number of clock cycles required to perform all required processing starting from a first time at which the value is read out of the cycle master node cycle timer (38) and ending with a second time at which the final adjusted cycle timer value is loaded into the cycle master node cycle timer (38); and,
adding the result of the above calculating sub-step to the adjusted cycle timer value, whereby the result of the adding step is the final adjusted cycle timer value.
9. The method as set forth in Claim 1, wherein:
the cycle master node (22) and the cycle slave node (20) are part of a first network; and,
the synchronization information is supplied by a second network that is external to the first network.
10. The method as set forth in Claim 1, wherein:
the cycle master node (22) and the cycle slave node (20) are part of a first sub-network; and,
the synchronization information is supplied by a second sub-network that is external to the first sub-network.
11. The method as set forth in Claim 3, wherein:
the cycle master node (22) and the cycle slave node (20) are part of a first sub-network which also includes a plurality of additional cycle slave nodes; and,
the cycle timer reset signal is synchronously supplied by a second sub-network that is external to the first sub-network.
12. The method as set forth in Claim 11, further including the step of regularly distributing the value of the cycle master node cycle timer (38) to all of the cycle slave nodes in the first sub-network, whereby all of the cycle slave nodes in the first sub-network are synchronized to the cycle timer reset signal.
13. The method as set forth in Claim 3, wherein:
the cycle master node (22) and the cycle slave node (20) are part of a first network which also includes a plurality of additional cycle slave nodes; and,
the cycle timer reset signal is synchronously supplied by a second sub-network that is external to the first network.
14. The method as set forth in Claim 13, further including the step of regularly distributing the value of the cycle master node cycle timer (38) to all of the cycle slave nodes in the first network, whereby the cycle timers of all of the cycle slave nodes in the first network are synchronized to the cycle timer reset signal.
15. A network (50), including:
a cycle master node (22) which includes a cycle master node cycle timer (38); and, cycle master node logic circuitry (32); and
a cycle slave node (20, 60) which includes a cycle slave node cycle timer (30) synchronized to the cycle master node cycle timer (38); and, cycle slave node logic circuitry (24);
wherein the cycle slave node logic circuitry (24) is responsive to synchronization information from an external network or sub-network to determine a timer offset value and to transmit the timer offset value to the cycle master node (22); and,
wherein the cycle master node logic circuitry (32) adjusts a value of the cycle master node cycle timer (38) on the basis of the timer offset value.
16. A network (50) as claimed in claim 15, including:
a first sub-network which includes a plurality of first nodes (Na) connected to a first local bus;
a second sub-network which includes a plurality of second nodes (Nb) connected to a second local bus;
a bridge which interconnects the first and second sub-networks, wherein the bridge includes:
a first bridge portal coupled to the first local bus and comprising the cycle slave node (20, 60);
a second bridge portal coupled to the second local bus and comprising the cycle master node (22); and,
an interconnect system (55) which interconnects the first and second bridge portals; and,
wherein a selected one of the first nodes (Na) which serves as a local cycle master of the first sub-network is a non-bridge node.
1. Verfahren zum Synchronisieren eines zyklischen Masterknotens (22) zu einem Sklavenknoten (20) in einem Netzwerk, wobei ein zyklischer Zeitgeber (30) in dem zyklischen Sklavenknoten zu einem zyklischen Zeitgeber (38) in dem zyklischen Masterknoten synchronisiert wird, wobei dieses Verfahren die nachfolgenden Verfahrensschritte umfasst:
- das Benutzen einer logischen Schaltung (24) in dem zyklischen Sklavenknoten (20) zum Ermitteln eines Zeitgeberoffsetwertes, und zwar in Reaktion auf den Empfang von Synchronisationsinformation von einem externen Netzwerk oder einem Subnetzwerk in dem zyklischen Sklavenknoten (20);
- das Übertragen des Zeitgeberoffsetwertes zu dem zyklischen Masterknoten (22); und
- das Benutzen der logischen Schaltung (32) in dem zyklischen Masterknoten (22) zum Einstellen eines Wertes des zyklischen Zeitgebers (38) des zyklischen Masterknotens auf Basis des Zeitgeberoffsetwertes.
2. Verfahren nach Anspruch 1, wobei die Synchronisationsinformation ein zyklisches Zeitgeberrückstellsignal umfasst.
3. Verfahren nach Anspruch 2, wobei:
der zyklische Zeitgeber (30) in dem zyklischen Sklavenknoten (20) während eines Zyklus von einem Ausgangswert bis einen Endwert zählt; und
das zyklische Zeitgeberrückstellsignal mit einer vorgeschriebenen Rate aufrechterhalten, die ein Vielfaches eines einzigen Zyklus des zyklischen Sklavenzykluszeitgebers (30) ist.
4. Verfahren nach Anspruch 3, wobei:
der zyklische Sklavenknoten (20) weiterhin ein Zeitgeberoffsetregister (26) aufweist;
der zyklische Masterknoten (22) weiterhin ein Zeitgebereinstellregister (34) aufweist;
der Schritt der Benutzung der logischen Schaltung (24) in dem zyklischen Sklavenknoten (20) zum ermitteln des Zeitgeberoffsetwertes die nachfolgenden Subschritte umfasst:
das Detektieren des zyklischen Zeitgeberrückstellsignals;
das Auslesen eines Wertes des zyklischen Zeitgebers (30) des zyklischen Sklavenknotens;
das Herleiten des Zeitgeberoffsetwertes von dem aus dem zyklischen Zeitgeber (30) des Sklavenknotens ausgelesenen Wert; und
das Laden des Zeitgeberoffsetwertes in das Zeitgeberoffsetregister (26).
5. Verfahren nach Anspruch 4, wobei der Schritt der Übertragung des Zeitgeberoffsetwertes zu dem zyklischen Masterknoten (22) die nachfolgenden Subschritte umfasst:
das Auslesen des Zeitgeberoffsetwertes aus dem Zeitgeberoffsetregister (20); und
das Senden des Zeitgeberoffsetwertes zu dem zyklischen Masterknoten (22), und zwar unter Anwendung eines asynchronen Datenübertragungsprotokolls.
6. Verfahren nach Anspruch 4, wobei der Schritt der Benutzung der logischen Schaltung (32) in dem zyklischen Masterknoten (22) zum Einstellen eines Wertes des zyklischen Zeitgebers (38) des zyklischen Masterknotens die nachfolgenden Subschritte umfasst:
das Laden des von dem zyklischen Sklavenknoten (20) empfangenen Zeitgeberoffsetwertes in das Zeitgebereinstellregister (34);
das Auslesen eines Wertes des zyklischen Zeitgebers (38) des zyklischen Masterknotens;
das Subtrahieren des Zeitgeberoffsetwertes von dem aus dem zyklischen Zeitgeber (38) des zyklischen Masterknotens ausgelesenen Wert zum Erzeugen eines eingestellten zyklischen Zeitgeberwertes;
das Herleiten eines schlussendlichen eingestellten zyklischen Zeitgeberwertes von dem eingestellten zyklischen Zeitgeberwert;
und,
das Laden des schlussendlichen eingestellten zyklischen Zeitgeberwertes in den zyklischen Zeitgeber (38) des zyklischen Masterknotens.
7. Verfahren nach Anspruch 4, wobei der Subschritt der Herleitung des Zeitgeberoffsetwertes von dem aus dem zyklischen Zeitgeber (30) des zyklischen Sklavenknotens die nachfolgenden Subschritte umfasst:
das Berechnen einer Anzahl Taktzyklen, die zwischen einem ersten Mal, wo das zyklische Zeitgeberrückstellsignal detektiert wurde, und einem zweiten Mal, wo der Wert aus dem zyklischen Zeitgeber (30) des zyklischen Sklavenknotens ausgelesen wurde, vergangen sind; und
das Subtrahieren des Ergebnisses des oben stehenden Berechnungsschrittes von dem aus dem zyklischen Zeitgeber (30) des zyklischen Sklavenknotens, wobei das Ergebnis des Subtrahierschrittes den Zeitgeberoffsetwert bildet.
8. Verfahren nach Anspruch 6, wobei der Subschritt der Herleitung des schlussendlichen eingestellten zyklischen Zeitgeberwertes die nachfolgenden Subschritte umfasst:
das Berechnen einer Anzahl Taktzyklen, erforderlich zum Durchführen der ganzen erforderlichen Verarbeitung, ausgehend von einem ersten Mal, wo der Wert aus dem zyklischen Zeitgeber (38) des zyklischen Masterknotens ausgelesen worden ist, und endend mit einem zweiten Mal, wo der schlussendliche eingestellte zyklische Zeitgeberwert in den zyklischen Zeitgeber (38) des zyklischen Masterknotens geladen worden ist; und
das Addieren des Ergebnisses des oben genannten Berechnungssubschrittes zu dem eingestellten zyklischen Zeitgeberwert, wobei das Ergebnis des Addierschrittes der schlussendliche eingestellte zyklische Zeitgeberwert ist.
9. Verfahren nach Anspruch 1, wobei:
der zyklische Masterknoten (22) und der zyklische Sklavenknoten (20) ein Teil eines ersten Netzwerkes sind; und
die Synchronisationsinformation von einem zweiten Netzwerk geliefert wird, das gegenüber dem ersten Netzwerk extern ist.
10. Verfahren nach Anspruch 1, wobei:
der zyklische Masterknoten (22) und der zyklische Sklavenknoten (20) ein Teil eines ersten Subnetzwerkes sind; und
die Synchronisationsinformation von einem zweiten Subnetzwerk geliefert wird, das gegenüber dem ersten Subnetzwerk extern ist.
11. Verfahren nach Anspruch 3, wobei:
der zyklische Masterknoten (22) und der zyklische Sklavenknoten (20) ein Teil eines ersten Subnetzwerkes sind, das auch eine Anzahl zusätzlicher zyklischer Sklavennetzwerke umfasst; und
das zyklische Zeitgeberrückstellsignal synchron von einem zweiten Subnetzwerk geliefert wird, das gegenüber dem ersten Subnetzwerk extern ist.
12. Verfahren nach Anspruch 11, das weiterhin den Schritt einer regelmäßigen Verteilung des Wertes des zyklischen Zeitgebers (38) des zyklischen Masterknotens über alle zyklischen Sklavenknoten in dem ersten Subnetzwerk umfasst, wobei alle zyklischen Sklavenknoten in dem ersten Subnetzwerk zu dem zyklischen Zeitgeberrückstellsignal synchronisiert sind.
13. Verfahren nach Anspruch 3, wobei:
der zyklische Masterknoten (22) und der zyklische Sklavenknoten (20) ein Teil eines ersten Netzwerkes sind, das auch eine Anzahl zusätzlicher zyklischer Sklavenknoten umfasst; und
das zyklische Zeitgeberrückstellsignal synchron von einem zweiten Subnetzwerk geliefert wird, das gegenüber dem ersten Netzwerk extern ist.
14. Verfahren nach Anspruch 13, das weiterhin den Schritt einer regelmäßigen Verteilung des Wertes des zyklischen Zeitgebers (38) des zyklischen Masterknotens über alle zyklischen Sklavenknoten in dem ersten Netzwerk umfasst, wobei die zyklischen Zeitgeber aller zyklischen Sklavenknoten in dem ersten Netzwerk zu dem zyklischen Zeitgeberrückstellsignal synchronisiert sind.
15. Netzwerk (50), das Folgendes umfasst:
einen zyklischen Masterknoten (22), der einen zyklischen Zeitgeber (38) des Masterknotens umfasst; und eine logischen Schaltung (32) des zyklischen Masterknotens; und
einen zyklischen Sklavenknoten (20, 60), der einen zyklischen Zeitgeber (30) des zyklischen Sklavenknotens umfasst, synchronisier zu dem zyklischen Zeitgeber (38) des zyklischen Masterknotens; und eine logische Schaltung (24) des zyklischen Sklavenknotens;
wobei die logische Schaltung (24) des zyklischen Sklavenknotens auf Synchronisationsinformation von einem externen Netzwerk oder einem Subnetzwerk reagiert, und zwar zum ermitteln eines Zeitgeberoffsetwertes und zum Übertragen des Zeitgeberoffsetwertes zu dem zyklischen Masterknoten (22); und
wobei die logische Schaltung (32) des zyklischen Masterknotens einen Wert des zyklischen Zeitgebers (38) des zyklischen Masterknotens einstellt, und zwar auf Basis des Zeitgeberoffsetwertes.
16. Netzwerk (50) nach Anspruch 15, das Folgendes umfasst:
ein erstes Subnetzwerk, das eine Anzahl erster Knoten (Na) aufweist, die mit einem ersten örtlichen Bus verbunden sind;
ein zweites Subnetzwerk, das eine Anzahl zweiter Knoten (Nb) aufweist, die mit einem zweiten örtlichen Bus verbunden sind;
eine Brücke, die das ersten und das zweite Subnetzwerk miteinander verbindet, wobei die Brücke Folgendes umfasst:
ein erstes Brückenportal, das mit dem ersten örtlichen Bus verbunden ist und den zyklischen Sklavenknoten (20, 60) enthält;
ein zweites Brückenportal, das mit dem zweiten örtlichen Bus verbunden ist und den zyklischen Masterknoten (22) enthält; und
ein Verbindungssystem (55), das das erste und das zweite Brückenportal miteinander verbindet; und
wobei ein selektierter Knoten der ersten Knoten (Na), der als örtliches zyklischer Master des ersten Subnetzwerkes wirksam ist, ein Nicht-Brückenknoten ist.
1. Procédé de synchronisation d'un noeud maître de cycle (22) sur un noeud esclave de cycle (20) dans un réseau, caractérisé en ce qu'un compteur de temps de cycle (30) du noeud esclave de cycle est synchronisé sur un compteur de temps de cycle (38) du noeud maître de cycle, comprenant les étapes suivantes :
utilisation de circuits logiques (24) dans le noeud esclave de cycle (20) pour déterminer une valeur de décalage de compteur de temps, en réponse au fait que le noeud esclave de cycle (20) reçoit des informations de synchronisation d'un réseau ou d'un sous-réseau externe;
transmission de la valeur de décalage du compteur de temps au noeud maître de cycle (22); et
utilisation de circuits logiques (32) dans le noeud maître de cycle (22) pour ajuster une valeur du compteur de temps de cycle de noeud maître de cycle (38) sur la base de la valeur de décalage du compteur de temps.
2. Procédé selon la revendication 1, caractérisé en ce que les informations de synchronisation comprennent un signal de réinitialisation de compteur de temps de cycle.
3. Procédé selon la revendication 2, caractérisé en ce que :
le compteur de temps de cycle (30) du noeud esclave de cycle (20) compte d'une valeur initiale à une valeur finale pendant un cycle; et
le signal de réinitialisation de compteur de temps de cycle est validé à une cadence prescrite qui est un multiple d'un cycle du compteur de temps de cycle (30) du noeud esclave de cycle.
4. Procédé selon la revendication 3, caractérisé en ce que :
le noeud esclave de cycle (20) comprend en outre un registre de décalage de compteur de temps (26);
le noeud maître de cycle (22) comprend en outre un registre d'ajustement de compteur de temps (34);
l'étape d'utilisation des circuits logiques (24) dans le noeud esclave de cycle (20) pour déterminer la valeur de décalage du compteur de temps comprend les sous-étapes suivantes :
détection du signal de réinitialisation du compteur de temps de cycle;
lecture d'une valeur du compteur de temps de cycle (30) du noeud esclave de cycle;
déduction de la valeur de décalage du compteur de temps à partir de la valeur lue dans le compteur de temps de cycle (30) du noeud esclave de cycle; et
chargement de la valeur de décalage du compteur de temps dans le registre de décalage de compteur de temps (26).
5. Procédé selon la revendication 4, caractérisé en ce que l'étape de transmission de la valeur de décalage du compteur de temps au noeud maître de cycle (22) comprend les sous-étapes suivantes :
lecture de la valeur de décalage du compteur de temps dans le registre de décalage de compteur de temps (26); et
envoi de la valeur de décalage du compteur de temps au noeud maître de cycle (22) en utilisant un protocole de transfert de données asynchrones.
6. Procédé selon la revendication 4, caractérisé en ce que l'étape d'utilisation des circuits logiques (32) dans le noeud maître de cycle (22) pour ajuster une valeur du compteur de temps de cycle (38) du noeud maître de cycle comprend les sous-étapes suivantes :
chargement de la valeur de décalage de compteur de temps reçue du noeud esclave de cycle (20) dans le registre d'ajustement de compteur de temps (34);
lecture d'une valeur du compteur de temps de cycle (38) du noeud maître de cycle;
soustraction de la valeur de décalage du compteur de temps à la valeur lue dans le compteur de temps de cycle (38) du noeud maître de cycle pour produire une valeur de compteur de temps de cycle ajustée;
déduction d'une valeur de compteur de temps de cycle ajustée finale à partir de la valeur de compteur de temps de cycle ajustée; et
chargement de la valeur de compteur de temps de cycle ajustée finale dans le compteur de temps de cycle (38) du noeud maître de cycle.
7. Procédé selon la revendication 4, caractérisé en ce que la sous-étape de déduction de la valeur de décalage du compteur de temps à partir de la valeur lue dans le compteur de temps de cycle (30) du noeud esclave de cycle comprend les sous-étapes suivantes :
calcul d'un nombre de cycles d'horloge qui se sont écoulés entre un premier instant lors duquel le signal de réinitialisation de compteur de temps de cycle à été détecté et un second instant lors duquel la valeur a été lue dans le compteur de temps de cycle (30) du noeud esclave de cycle; et
soustraction du résultat de l'étape de calcul mentionnée ci-dessus à la valeur lue du compteur de temps de cycle (30) du noeud esclave de cycle, le résultat de l'étape de soustraction constituant la valeur de décalage du compteur de temps.
8. Procédé selon la revendication 6, caractérisé en ce que la sous-étape de déduction de la valeur de compteur de temps de cycle ajustée finale comprend les sous-étapes suivantes :
calcul d'un nombre de cycles d'horloge exigés pour effectuer la totalité du traitement depuis un premier instant lors duquel la valeur du compteur de temps de cycle (38) du noeud maître de cycle est lue et se terminant à un second instant lors duquel la valeur du compteur de temps de cycle ajustée finale est chargée dans le compteur de temps de cycle (38) du noeud maître de cycle; et
addition du résultat de la sous-étape de calcul mentionnée ci-dessus à la valeur du compteur de cycle ajustée, le résultat de l'étape d'addition étant la valeur du compteur de temps de cycle ajustée finale.
9. Procédé selon la revendication 1, caractérisé en ce que :
le noeud maître de cycle (22) et le noeud esclave de cycle (20) font partie d'un premier réseau; et
les informations de synchronisation sont délivrées par un second réseau qui est extérieur au premier réseau.
10. Procédé selon la revendication 1, caractérisé en ce que :
le noeud maître de cycle (22) et le noeud esclave de cycle (20) font partie d'un premier sous-réseau; et
les informations de synchronisation sont délivrées par un second sous-réseau qui est extérieur au premier sous-réseau.
11. Procédé selon la revendication 3, caractérisé en ce que :
le noeud maître de cycle (22) et le noeud esclave de cycle (20) font partie d'un premier sous-réseau qui comprend également une pluralité de noeuds esclaves de cycle supplémentaires; et
le signal de réinitialisation du compteur de temps de cycle est délivré de façon synchrone par un second sous-réseau qui est extérieur au premier sous-réseau.
12. Procédé selon la revendication 11, comprenant en outre l'étape visant à distribuer régulièrement la valeur du compteur de temps de cycle (38) du noeud maître de cycle à tous les noeuds esclaves de cycle dans le premier sous-réseau, tous les noeuds esclaves de cycle du premier sous-réseau étant synchronisés sur le signal de réinitialisation du compteur de temps de cycle.
13. Procédé selon la revendication 3, caractérisé en ce que :
le noeud maître de cycle (22) et le noeud esclave de cycle (20) font partie d'un premier réseau qui comprend également une pluralité de noeuds esclaves de cycle supplémentaires; et
le signal de réinitialisation de compteur de temps de cycle est délivré de façon synchrone par un second sous-réseau qui est extérieur au premier sous-réseau.
14. Procédé selon la revendication 13, comprenant en outre l'étape de distribution régulière de la valeur du compteur de temps de cycle (38) du noeud maître de cycle à tous les noeuds esclaves de cycle du premier réseau, les compteurs de temps de cycle de tous les noeuds esclaves de cycle du premier réseau étant synchronisés sur le signal de réinitialisation du compteur de temps de cycle.
15. Réseau (50), comprenant :
un noeud maître de cycle (22) qui comprend un compteur de temps de cycle (38) de noeud maître de cycle;
des circuits logiques de noeuds maîtres de cycle (32); et
un noeud esclave de cycle (20, 60) qui comprend un compteur de temps de cycle (30) de noeud esclave de cycle synchronisé sur le compteur de temps de cycle (38) du noeud maître de cycle; et des circuits logiques de noeuds esclaves de cycle (24);
caractérisé en ce que les circuits logiques de noeuds esclaves de cycle (24) sont sensibles à des informations de synchronisation provenant d'un réseau ou d'un sous-réseau externe pour déterminer une valeur de décalage de compteur de temps et pour transmettre la valeur de décalage de compteur de temps au noeud maître de cycle (22); et
en ce que les circuits logiques de noeuds maîtres de cycle (32) ajustent une valeur du compteur de temps de cycle (38) du noeud maître de cycle sur la base de valeur de décalage du compteur de temps.
16. Réseau (50) selon la revendication 15, comprenant :
un premier sous-réseau qui comprend une pluralité de premiers noeuds (Na) connectés à un premier bus local;
un second sous-réseau qui comprend une pluralité de seconds noeuds (Nb) connectés à un second bus local;
un pont qui interconnecte les premiers et seconds sous-réseaux, caractérisé en ce que le pont comprend :
un premier portail de pont relié au premier bus local et comprenant le noeud esclave de cycle (20, 60);
un second portail de pont relié au second bus local et comprenant le noeud maître de cycle (22); et
un système d'interconnexion (55) qui interconnecte les premier et second portails de ponts; et
caractérisé en ce que l'un, sélectionné, des premiers noeuds (Na) qui sert de maître de cycle local du premier sous-réseau est un noeud autre qu'un pont.