Semiconductor memory device

(19)

(11)

EP 0 991 077 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	05.07.2000 Bulletin 2000/27

(43)	Date of publication A2:
	05.04.2000 Bulletin 2000/14

(21)	Application number: 99124040.9

(22)	Date of filing: 31.01.1995

(51)	International Patent Classification (IPC)⁷: G11C 8/00

(84)	Designated Contracting States:
	DE FR GB

(30)

Priority:

31.01.1994 JP 892194
23.01.1995 JP 847195

(62)	Application number of the earlier application in accordance with Art. 76 EPC:
	95101293.9 / 0665556

(71)	Applicant: KABUSHIKI KAISHA TOSHIBA
	Kawasaki-shi, Kanagawa-ken 210-8572 (JP)

(72)	Inventor:
	Kohno, Fumihiro, Intellectual Property Division Minato-ku, Tokyo 105-8001 (JP)

(74)	Representative: HOFFMANN - EITLE
	Patent- und Rechtsanwälte Arabellastrasse 4 81925 München 81925 München (DE)

(54)	Semiconductor memory device

(57) The invention relates to a semiconductor memory device including a plurality of memory cells (10); a word line (WLO) connected to the plurality of memory cells (10) ;a boosted voltage generating circuit (14) which generates a constant boosted potential (VPP) higher than a power-supply potential (VCC); a level-shiftig circuit (15) which level-shifts a precharge signal (PRCH) using the power-supply potential (VCC) to a boosted precharge signal (PRCH') using the constant boosted potential (VPP); a decoder circuit having address signal input terminals to which address signals (A0, A1, AK) are inputted; a circuit having an inverter circuit (30-0, 18-0), a P-channel transistor (28-0) and an input terminal, the inverter circuit (30-0, 18-0) comprising an input terminal connected to the output terminal of the decoder circuit (13-0) and an output terminal; and a word line driving circuit (11-0) which drives the word (WL0) in accordance with a potential at the output terminal of the circuit.

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