DRAM memory array with four cells per bit line contact

(19)

(11)

EP 0 991 124 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	14.12.2005 Bulletin 2005/50

(43)	Date of publication A2:
	05.04.2000 Bulletin 2000/14

(21)	Application number: 99116439.3

(22)	Date of filing: 21.08.1999

(51)	International Patent Classification (IPC)⁷: H01L 27/108

(84)	Designated Contracting States:
	AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
	Designated Extension States:
	AL LT LV MK RO SI

(30)

Priority:

30.09.1998 US 163670

(71)	Applicant: Infineon Technologies AG
	81669 München (DE)

(72)	Inventor:
	Hieke, Andreas, Dr. Wappingers Falls,NY 12590 (US)

(74)	Representative: Patentanwälte Westphal, Mussgnug & Partner
	Am Riettor 5 78048 Villingen-Schwenningen 78048 Villingen-Schwenningen (DE)

(54)	DRAM memory array with four cells per bit line contact

(57) A cell-quadropole cell structure is disclosed which extends the principle of sharing the bitline-stud between two different cells (arranged in a one-dimensional line, e.g. w-direction) further to the maximal possible degree of a sharing in a two-dimensional area (x- and y-direction) consequently forming a cross of four cells around one bitline-stud (10) with each drain region and buried strap (8) extended to the side and the trench (7) attached forming a hook like structure.

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