CMOS DELAY CIRCUIT USING SUBSTRATE BIASSING - Patent 1016212

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EP 1 016 212 A1

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(43)	Date of publication:
	05.07.2000 Bulletin 2000/27

(21)	Application number: 99931253.1

(22)	Date of filing: 02.07.1999

(51)	International Patent Classification (IPC)⁷: H03K 5/13

(86)	International application number:
	PCT/EP9904/708

(87)	International publication number:
	WO 0004/638 (27.01.2000 Gazette 2000/04)

(84)	Designated Contracting States:
	AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

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Priority:

14.07.1998 EP 98202357

(71)	Applicant: Koninklijke Philips Electronics N.V.
	5621 BA Eindhoven (NL)

(72)	Inventors:
	MESSMER, Adrian NL-5656 AA Eindhoven (NL) SCHELLER, Gerd, J., E. NL-5656 AA Eindhoven (NL)

(74)	Representative: Duijvestijn, Adrianus Johannes
	Internationaal Octrooibureau B.V.,Prof. Holstlaan 6 5656 AA Eindhoven 5656 AA Eindhoven (NL)

(54)	CMOS DELAY CIRCUIT USING SUBSTRATE BIASSING