An oscillation circuit 80 produces an oscillation signal in accordance with the oscillation frequency of a quartz oscillator 81, and a frequency dividing circuit 90 divides the frequency of the oscillation signal to produce a sampling clock CKs having a duty ratio of 1/8. A constant-voltage circuit 70 is operated during the period in which the sampling clock CKs takes an "H" level, and is stopped during the period in which the sampling clock CKs takes an "L" level. During the period in which the constant-voltage circuit 70 stops the operation, a voltage Vreg affected by fluctuations in a second lower potential side voltage Vss2 is generated. However, since the cycle of the sampling clock CKs is short, a fluctuation width of the voltage Vreg is suppressed. Power consumption of the constant-voltage circuit 70 is reduced to 1/8 of that in the case of operating the circuit 70 at all times.