(19)
(11) EP 1 064 767 B8

(12) CORRECTED EUROPEAN PATENT SPECIFICATION
Note: Bibliography reflects the latest situation

(15) Correction information:
Corrected version no 1 (W1 B1)

(48) Corrigendum issued on:
27.06.2007 Bulletin 2007/26

(45) Mention of the grant of the patent:
16.05.2007 Bulletin 2007/20

(21) Application number: 99911237.8

(22) Date of filing: 08.03.1999
(51) International Patent Classification (IPC): 
H04L 25/06(2006.01)
 H04L 25/02(2006.01)
(86) International application number:
PCT/US1999/005120
(87) International publication number:
WO 1999/048260 (23.09.1999 Gazette 1999/38)

(54)

HIGH SPEED SIGNALING FOR INTERFACING VLSI CMOS CIRCUITS

HOCHGESCHWINDIGKEITSSIGNALISIERUNG ZUR SCHNITTSTELLENBILDUNG VON VLSI CMOS-SCHALTUNGSANORDNUNGEN

SIGNALISATION RAPIDE PERMETTANT L'INTERFA AGE DE CIRCUITS VLSI CMOS

(84) Designated Contracting States:
AT BE CH CY DE DK ES FI FR GR IE IT LI LU MC NL PT SE
Designated Extension States:
AL LT LV MK RO SI

(30) Priority: 16.03.1998 US 78213 P
07.04.1998 US 57158
02.10.1998 US 165705

(43) Date of publication of application:
03.01.2001 Bulletin 2001/01

(73) Proprietor: Jazio Inc.
San José, California 95110 (US)

(72) Inventor:
  • EJAZ, Ul, Haq
    Sunnyvale, CA 94087 (US)

(74) Representative: Haines, Miles John L.S. et al
D Young & Co 120 Holborn
London EC1N 2DY
London EC1N 2DY (GB)


(56) References cited: : 
WO-A-92/17938
US-A- 5 473 635
 US-A- 5 355 391
US-A- 5 715 405
   
  • IEEE STANDARD FOR LOW-VOLTAGE DIFFERENTIAL SIGNALS (LVDS) FOR SCALABLE COHERENT INTERFACE (SCI) - IEEE STD 1596.3-1996, 1996, XP002106653 New York, US cited in the application
   
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).