Circuit for the compression of the dynamic range of a signal

Description

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a circuit for compressing the dynamic range of the power of input signals to a transmitting signal amplifier and a receiving amplifier, and a power amplifying circuit using the dynamic range compressing circuit.

[0002] Recently multi-carrier radio communication schemes are widespread which permit high-speed transmission possible the use of plural narrow-band carriers. As compared with a single-carrier high-speed transmission, the multi-carrier high-speed transmission is less susceptible to fading or some other influences of changes in the propagation path, and hence is more robust against delay waves. Furthermore, the multi-carrier system possesses the advantages of simplifying radio circuitry and relaxing the requirements imposed on the radio circuit used.

[0003] The multi-carrier radio communication schemes, thus suitable for the high-speed transmission, have been practiced in fixed microwave communication systems and multi-channel access systems.

[0004] In recent years there has been proposed an OFDM (Orthogonal Frequency Division Multiplexing) radio communication scheme intended for high-speed transmission in the microwave band such as 5-GHz band on IEEE802.11. In the field of broadcasting the application of the OFDM system to the next-generation digital television is now under study.

[0005] These multi-carrier radio communication schemes contain various features, but have such problems as an increase in out-of-band leakage power due to intermodulation distortion and the occurrence of intersymbol interference by nonlinearity of transmitters. The intermodulation distortion on transmitters occurs, for example, in a frequency converter or power amplifier. In particular, the influence of the nonlinearity of the power amplifier is great. In general, simultaneous amplification of multi-carrier will generate the intermodulation distortion if no output back-off is provided corresponding to PAPR (Peak-to-Average Power Ratio). Accordingly, the power amplifier for the multi-carrier transmission needs to be sufficiently high saturation output. Usually, the power amplifier becomes bulky and expensive with an increase in the saturation output because it involves an increase of the power supply and upsizing of radiation fins.

[0006] Heretofore, 4-carrier 16-QAM and 4-carrier 256-QAM systems have been put into use in the fixed microwave communication. The power amplifier in these systems combines individually amplified signals by a signal multiplexer having a quarter-wave line. The individual amplification of plural carriers is intended to avoid the problem of increased PAPR resulting from the multiplexing of the plural carriers.

[0007] Schemes that have been proposed so far to suppress PAPR in the multi-carrier transmission are: a scheme for setting initial phases of carriers (Shoichi NARAHASHI and Toshio NOJIMA, "A New Phasing Scheme for Multitone Signal systems to Reduce Peak-to-Average-Power Ratio (PAPR)," The Institute of Electronics, Information and Communication Engineers Transaction on B-II, Vol. J78-B-II, No. 11, pp.663-671, Nov., 1955); a scheme using a specific signal pattern that produces no peak (U.S. Patent No. 5,381,449, "Peak-to-average-power ratio reduction methodology for QAM communications system); a scheme using an error correcting code (T.A. Wilkinson and A.E. Jones, "Minimisation of the peak to mean envelope power ratio of multicarrier transmission schemes by block coding," in Proc. 45th IEEE Vechi. Technol. Conf., pp.825-829, 1995); a scheme of multiplexing peak power suppressing signals (Shigeru TOMOSATO and Hiroshi SUZUKI, "A Smooth Envelope Parallel Modulation/Demodulation Scheme," Technical Report of IEICE, RCS 95-77, Sept., 1995); and a scheme using orthonormal transformation (Japanese Patent Application Laid-Open Gazette No. 10-178411, corresponding U.S. Patent Application Serial No. 08/948,090). In particular, there are known, as PAPR suppression schemes for OFDM, a scheme of clipping a multiplexed signal waveform (X. Li and L.J. Cimni, Jr., "Effects of Clipping and Filtering on the Performance of OFDM," in Proc., 47th IEEE Vechi. Technol. Conf., pp.1634-1638, 1997) and a scheme of effecting transmitting output control according to peak power (Yoichi MATSUMOTO, Nobuaki MOCHIZUKI and Masahiro UMEHIRA, "A Novel Peak Power Reduction Technique for Broadband Microcellular OFDM systems," Technical Report of IEICE, RCS 97-143, Oct., 1997).

[0008] The requirement for PAPR reduction in the multi-carrier radio communication is to prevent degradation of transmission performance without increasing the out-of-band power leakage. In terms of this requirement, the clipping of a multiplexed signal waveform causes an increase in the out-of-band power leakage. The control of the transmitting output according to peak power encounters difficulty in maintaining channel quality. The initial phase setting scheme is difficult to apply to a modulated wave of ever-changing phase. The utilization of orthonormal transformation is defective in that phase fluctuations of carriers degrade the inter-carrier orthogonality, resulting in the development of peak power. The use of an error correcting code and the multiplexing of peak power suppressing signals both involve enlargement of the transmission band. Thus, the conventional PAPR reduction schemes have such problems as the enlargement of the transmission band, difficulty in the application to modulated waves, an increase in the out-of-band distortion and difficulty in maintaining channel quality.

[0009] And, peak power reduction schemes applicable to modulated waves all involve signal processing of suppressing the peak power at the transmitting side and signal processing of reconstructing the received signal at the receiving side. To allow ease in the fabrication of a peak power suppressing circuit and achieve high-efficiency amplification that permits reduction in the size, weight and power consumption of the power amplifier, it is desirable to use a peak power suppression scheme that can be carried out within only the transmitting side as much as possible. In this respect, the initial phase setting scheme and a scheme using a PAPR reduction signal point are effective, but the former is difficult to apply to modulated waves and the latter is limited in the application to transmitting signal sequences.

[0010] A signal power dynamic range compressing circuit according to the pre-characterizing portion of claim 1 is known from May T et al: "Reducing the peak-to-average power ratio in OFDM radio transmission system", Vehicular Technology Conference, 1998, VTC98; 48th IEEE OTTAWA, ONT., CANADA, 18-21 May 1998, New York, NY, USA, IEEE, US, 18 May 1998, pages 2474-2478, XP010288142. In this prior art, a correcting function k(t) is added to an input signal s(t) whereby the amplitude of the input signal s(t) exceeding A₀ at temporal positions t_n is limited to A₀. The correcting function k(t) is added to the input signal s(t) only when the amplitude of input signal s(t) exceeds a threshold value. When the amplitude of the input signal s(t) is below the threshold value, the correcting function k(t) is not added. This correction operation could cause the signal to exceed the amplitude threshold A₀ at different positions. The prior art ignores this.

SUMMARY OF THE INVENTION

[0011] It is an object of the present invention is to provide an input signal power dynamic range compressing circuit that develops no out-of-band power leakage of the input signal thereto and permits effective compression of the signal power dynamic range irrespective of phase variations of the input signal, and a power amplifying circuit using the dynamic range compressing circuit.

[0012] This object is achieved by a signal power dynamic range compressing circuit as claimed in claim 1. Preferred embodiments of the invention are subject-matter of the dependent claims.

[0013] A power amplifier is connected to the output of the signal power dynamic range compressing circuit to form a power amplifying circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] 

Fig. 1 is a block diagram illustrating the basic configuration of the present invention;

Fig. 2 is a diagram showing the vector of the input to a power amplifier, for explaining the principle of operation of the present invention;

Fig. 3 is a graph depicting the spectrum of the input signal to the power amplifier;

Fig. 4 is a graph showing the spectrum of an output signal from the power amplifier;

Fig. 5 is a block diagram illustrating a first embodiment of the present invention;

Fig. 6 is a graph conceptually showing operation characteristics, for explaining the amplification efficiency of a power amplifier embodying the present invention;

Fig. 7 is a block diagram illustrating a second embodiment of the present invention;

Fig. 8 is a block diagram illustrating a third embodiment of the present invention;

Fig. 9 is a block diagram illustrating a fourth embodiment of the present invention;

Fig. 10 is a block diagram illustrating a fifth embodiment of the present invention;

Fig. 11 is a block diagram illustrating a sixth embodiment of the present invention;

Fig. 12 is a graph showing the spectrum of the input to the amplifier when a CDMA signal is injected, as a compressing signal, into the same band as that of the input;

Fig. 13 is a graph showing the spectrum of the output from the amplifier when the CDMA signal is injected into the same band as that of the input;

Fig. 14 is a graph showing the spectrum of the input to the amplifier when a carrier signal is injected, as a compressing signal, into the same band as that of the input signal;

Fig. 15 is a graph showing the spectrum of the output from the amplifier when the carrier signal is injected into the same band as that of the input signal;

Fig. 16 is a graph showing the spectrum of the input to the amplifier when the carrier signal is injected, as a compressing signal, into a band different from that of the input signal;

Fig. 17 is a graph showing the spectrum of the output from the amplifier when the carrier signal is injected into a band different from that of the input signal;

Fig. 18 is a block diagram illustrating a seventh embodiment of the present invention;

Fig. 19 is a block diagram illustrating an eighth embodiment of the present invention;

Fig. 20 is a block diagram illustrating a ninth embodiment of the present invention;

Fig. 21 is a block diagram illustrating a tenth embodiment of the present invention;

Fig. 22 is a block diagram illustrating an eleventh embodiment of the present invention;

Fig. 23 is a block diagram illustrating a twelfth embodiment of the present invention; and

Fig. 24 is a block diagram illustrating a thirteenth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] In Fig. 1 there is depicted in block form the basic configuration of the signal power dynamic range compressing circuit according to the present invention and the power amplifying circuit using it.

[0016] In Fig. 1, the signal power dynamic range compressing circuit, indicated generally by 100, comprises a directional coupler 2, a linear signal transfer path 21, a compressing signal generating path 22, and a power combiner 6. Fig. 1 depicts the case where the output of the power combiner 6 is connected to a power amplifier 8 to form a power amplifying circuit. The directional coupler 2 divides an input signal S_IN at an input terminal TI to the two paths 21 and 22. The directional coupler 2 may be a power divider, but the following embodiments will be all described to use the directional coupler 2. The one path 21 is a linear signal transfer path formed by a delay line 3, whereas the other path 22 is a compressing signal generating path containing a compressing signal generator 4. The compressing signal generator 4 detects the power of the input signal S_IN, and generates a signal for compressing the output back-off of the power amplifier 8 (which signal will hereinafter be referred to as a compressing signal) S_PC. The compressing signal S_PC is combined by the power combiner 6 with an output S_D from the delay line 3 to form a combined signal S_C for compressing the output back-off of the power amplifier 8. The combined signal S_C is applied to the power amplifier 8, and the compressing signal S_PC injected at the input thereof is eliminated by a compressing signal canceling circuit 10 connected to the output of the power amplifier 8.

[0017] Referring next to Fig. 2, a description will be given of the principle of operation of the present invention. Fig. 2 depicts the vector of the input signal to the power amplifier 8 in the case where respective modulated signals were subjected to orthogonal detection.

[0018] The compressing signal generating circuit 4 is a circuit that generates the compressing signal S_PC whose vector S_PC is combined with the output vector S_D of the linear signal transfer path 21 into the combined vector S_C. As described later on, there are two kinds of such compressing signal generating circuits: a circuit for generating the compressing signal S_PC that compresses the peak power of the input signal and a circuit for generating the compressing signal S_PC that compresses the peak-to-average-power ratio.

[0019] In the case of suppressing the peak power, the compressing signal generator 4 generates the compressing signal vector S_PC that is nearly 180° out of phase with the input signal vector S_IN (and consequently the signal vector S_D corresponding thereto) as depicted in Fig. 2. The compressing signal vector S_PC is produced, as described later on, by detecting the peak power of the amplifier input signal, then detecting the amplitude and phase of the input signal and generating a vector having the amplitude of the signal vector S_D held constant. In the example of Fig. 1, a tone signal (a single-frequency signal) 180° out of phase with the input signal is generated by a low-frequency oscillator in the compressing signal generator 4. As a result, the magnitude of the combined vector by the directional coupler 6 can be made constant. Having thus generated the compressing signal S_PC, the compressing signal generator 4 holds its output until the next detection of a peak power equal to or larger than a preset threshold value. In this way, upon each detection of the peak power, the vector nearly 180° out of phase with the input signal is generated and combined with the output signal S_D from the linear signal transfer path 21 to obtain the combined signal S_C having its peak power suppressed, and the combined signal S_C is applied to the power amplifier 8. By such reduction of the peak power of the input signal, it is possible to obtain the combined signal S_C in which the power dynamic range of the input signal S_IN is suppressed within a desired range.

[0020] The compressing signal S_PC by the compressing signal generator 4 is a single-frequency signal (which will hereinafter be referred to also as a tone signal). The compressing signal S_PC is frequency-converted to a band different from or identical with that of the input signal S_IN. Figure 3 depicts an example in which the compressing signal S_PC is frequency-converted to a different band from that of the input signal S_IN. As shown, the input signal S_IN of amplifier and the compressing signal S_PC lie in different bands. Figure 4 depicts the output spectrum of the power amplifier 8. If necessary, a band-pass filter (BPF) is provided as the compressing signal canceller 10 at the output side of the power amplifier 8 so that the compressing signal injected at the input side of the power amplifier 8 is eliminated by the frequency characteristic of the band-pass filter.

[0021] In this way, the peak power of the transmitting signal is suppressed, then its power is amplified by the power amplifier 8, and the component of the compressing signal S_PC is eliminated by the band-pass filter 10, by which it is possible to offer a peak power reduction scheme that is completed within the transmitting circuit. Accordingly, the suppression of the peak power of the input to the power amplifier 8 reduces its output back-off, permitting high-efficiency amplification. Of course, the vector of the compressing signal that is generated in the interval between the points of detection of the peak power of the input signal is held constant, but the input signal vector varies; therefore, their combined vectors do not always become constant.

[0022] While Fig. 3 and 4 are shown to use a tone signal, a modulating wave can be used as the compressing signal S_PC.

[0023] Next, a description will be given of the operation of the compressing signal generator 4 in the case of suppressing the PAPR. The basic principle of operation is the same as that for suppressing the peak power, but the compressing signal S_PC is used to reduce the PAPR of the input signal S_IN in this instance. The generation of the compressing signal S_PC begins with the detection of the PAPR of the input signal S_IN, and if the detected ratio is equal to or higher than a preset value, the vector of the compressing signal S_PC is determined by the compressing signal generator 4 so that the PAPR of the combined signal S_C is equal to or lower than a prescribed value. As a result, the combined signal S_C can be obtained by suppressing the PAPR of the input signal S_IN. The signal S_PC for suppressing the PAPR is frequency-converted to a different band from or identical with that of the input signal S_IN. The compressing signal S_PC can be cancelled, if necessary, by the band-pass filter 10 at the output side of the power amplifier 8. To reduce the PAPR of the input signal S_IN, the vector of the compressing signal S_PC is determined in such a manner as to increase and/or decrease the average power relative to, for example, the peak power.

[0024] The compressing signal S_PC for suppressing the PAPR may be generated so that the amplitude of the combined signal S_C takes a predetermined fixed value sufficiently smaller than a predicted peak of the input signal S_IN. Figure 2 shows the locus of the signal in an IQ plane which is obtained by the orthogonal detection of the combined signal S_C. In this case, the envelope of the combined signal S_C takes a constant value as indicated by the circle in Fig. 2. In the embodiments described later on this compressing signal S_PC is called a constant envelope signal.

[0025] Such reduction of the PAPR of the transmitting signal permits suppression of the input signal power dynamic range of the power amplifier 8. Further, it is possible to provide a PAPR suppression scheme that is completed within the transmitting circuit. Besides, the suppression of the PAPR of the amplifier input signal reduces the output back-off, allowing high-efficiency amplification.

FIRST EMBODIMENT

[0026] Figure 5 illustrates in block form a first embodiment of the present invention in which the basic configuration of the signal power dynamic range compressing circuit shown in Fig. 1 is applied to the peak power suppression. The amplifier input signal S_IN is divided by the directional coupler 2 to the linear signal transfer path 21 formed by the delay line 3 and the compressing signal generating path 22 formed by the compressing signal generator 4. The compressing signal generator 4 is formed by a cascade connection of a level discriminator 41, a peak power detector 42, a low-frequency oscillator 44, a frequency converter 45, a variable phase shifter 46 and a variable amplifier 47V. The level discriminator 41 observes an instantaneous value of the amplitude of the distributed input signal S_IN. The observed instantaneous value is compared with a threshold value preset in the level discriminator 41, and only when the former is equal to or larger than the latter, the distributed input signal S_IN is fed to the peak power detector 42. The peak power detector 42 is formed by an orthogonal demodulator, which performs orthogonal detection of the input signal S_IN fed from the output of the level discriminator 41, detecting the vector (amplitude and phase values) of the input signal S_IN. The thus detected amplitude and phase values are input to the low-frequency oscillator 44.

[0027] The low-frequency oscillator 44 is formed by a synthesizer in which the amplitude and phase values can be set. To suppress the input power dynamic range of the power amplifier 8, the low-frequency oscillator 44 is set so that its oscillation signal is nearly 180° out of phase with the detected phase value; that is, the phase that is set in the low-frequency oscillator 44 is opposite to the phase detected by the peak power detector 42. And the amplitude value is chosen such that the combined signal S_C estimated by the peak power detector 42 through numerical calculations will have a constant envelope. This permits generation of the compressing signal S_CC of a vector that suppresses the peak power. The synthesizer output is frequency-converted by the frequency converter 45 to a predetermined band, which may be the same as or different from the band of the amplifier input signal S_IN. The frequency-converted compressing signal is subjected to final adjustments of its amplitude and phase by the variable phase shifter 46 and the variable amplifier 47V. The thus finally adjusted compressing signal S_PC is combined in power by the power combiner 6 with the signal S_D from the delay line 3. As the result of this, the peak power of the input signal is reduced. In this embodiment the power combiner 6 divides the combined signal S_C. The power of the combined signal S_C is mostly distributed to the power amplifier 8 and partly to a control path. The variable amplifier 47V may also be composed of a variable attenuator and an amplifier.

[0028] In the basic configuration depicted in Fig. 1, upon detection of the peak power of the input signal S_IN, it is suppressed by the compressing signal S_PC opposite in phase thereto, but since the vector of the input signal S_IN varies with time, there is the possibility that the instantaneous amplitude value of the combined signal S_C exceeds the afore-mentioned predetermined threshold value before the next peak power of the input signal S_IN is detected by the level discriminator 41.

[0029] To avoid this, the Fig. 5 embodiment uses a compressing signal adjustment part 11 in the control path 23 by which to keep the level of the combined signal S_C from exceeding the threshold value. The compressing signal adjustment part 11 is formed by a cascade connection of a level discriminator 15, a peak power detector 16 and a control circuit 17. The level discriminator 15 decides whether the peak power of the distributed combined signal S_C is in excess of a predetermined threshold value, and if so, transfers the combined signal S_C to the peak power detector 16. The peak power detector 16 performs orthogonal detection of the combined signal S_C fed thereto to detect its phase and amplitude, and provides them to the control circuit 17. Based on the phase and amplitude thus detected, the control circuit 17 controls the phase shift amount of the variable phase shifter 46 and the amplification factor of the variable amplifier 47V by an adaptive algorithm on a stepwise basis so that the peak power of the combined signal S_C becomes smaller than the threshold value.

[0030] The control circuit 17 is formed by a microcomputer, which controls the variable phase shifter 46 and the variable amplifier 47 by a perturbation algorithm, least square estimation algorithm, or the like. The control operation of the control circuit 17 may be implemented by a digital or analog circuit. The variable amplifier 47V may be replaced with a variable attenuator, which produces the same peak voltage suppression effect. The amplitude and phase values of the low-frequency oscillator 44 may also be placed under the control of the control circuit 17.

[0031] According to this embodiment, since the power dynamic range of the input signal S_IN can be reduced by the adaptive suppression of its peak power, the output back-off of the power amplifier 8 can be reduced. This enables the power amplifier 8 to achieve high-efficiency amplification.

[0032] Figure 6 shows, in terms of drain efficiency, the amplification efficiency that is improved by connecting the signal power dynamic range compressing circuit of the present invention to the input side of the power amplifier 8. For example, in the case of an input signal with a 10-dB PAPR, a 4-dB suppression of the peak power will provide a 6-dB PAPR reduction of the input combined signal S_C to the power amplifier 8. This permits reduction of a 10-dB output back-off down to 6 dB prior to the suppression of the peak power. The 4-dB suppression of the peak power has such an influence on the amplification efficiency of the power amplifier 8 as described below. Assuming that the amplifier 8 is a class "A" amplifier whose maximum drain efficiency at the saturation output point is 50%, and whose output back-off is defined to be the difference between a 1-dB gain compression point and the operating point, the drain efficiency can be improved to about 10% by the application of the present invention, whereas the drain efficiency is 4% or so when the present invention is not used. Thus, even if the peak power is not completely suppressed, the present invention is effective in improving the amplification efficiency of the power amplifier 8. And this does not ever generate either out-of-band leakage of power or intersymbol interference.

SECOND EMBODIMENT

[0033] Figure 7 illustrates in block form a second embodiment of the present invention, in which the peak power detector 42 of the compressing signal generator 4 in Fig. 5 is formed by a peak power detector 43 which measures the peak power of the input signal S_IN, such as a diode sensor or thermocouple. The peak power detector 43 detects only the peak power of the input signal S_IN and does not detect its phase value. Accordingly, the low-frequency oscillator 44 oscillates in a suitable initial phase. The output from the power combiner 6 is provided via the level discriminator 15 and the peak power detector 16 to the control circuit 17, which controls the phase value of the variable phase shifter 46 and the amplitude value of the variable amplifier 47 on a stepwise basis until the minimum peak power is detected. The arrangement of this embodiment permits simplification of the configuration of the peak power detector.

THIRD EMBODIMENT

[0034] Figure 8 illustrates in block form a third embodiment of the present invention. While the embodiments of Figs. 5 and 7 have been described to use a band-pass filter as the compressing signal canceller 10 for canceling the compressing signal in the output from the power amplifier 8, the Fig. 8 embodiment does not employ the band-pass filter but has a construction in which a elimination signal S_CC is generated by reversing the phase of the compressing signal S_PC and is injected into the output from the power amplifier 8 to cancel the compressing signal component. A combined signal generator 9, which constitutes a path for canceling the compressing signal component, is formed by a cascade connection of a phase inverter 91, a variable phase shifter 92 and a variable amplifier 93. The phase inverter 91 inverts the phase of the compressing signal S_PC is divided by the directional coupler 18, and outputs the phase-inverted signal as the elimination signal S_CC.

[0035] The variable phase shifter 92 and the variable amplifier 93 are controlled by a control circuit 53 on a stepwise basis to adjust the phase and amplitude of the elimination signal S_CC. The output from the power amplifier 8 and the elimination signal S_CC are combined/distributed by a power combiner/distributor 10, and the combined output power is mostly provided to an output terminal TO and partly to a combined signal adjustment part 50 for monitor use. The elimination signal adjustment part 50 is formed by a cascade connection of a level discriminator 51, a peak power detector 52 and the control circuit 53. The elimination signal adjustment part 50 operates in the same manner as does the compressing signal adjustment part 11, and adjusts the phase and amplitude of the elimination signal S_CC to control the variable phase shifter 92 and the variable amplifier 93 on a step-by-step basis until the level of the residual compressing signal component in the output from the power amplifier 8 goes down below a predetermined field intensity. The variable amplifier 93 for adjusting the amplitude component may be replaced with a variable attenuator.

[0036] This embodiment is suitable for use in the case where the injected carrier cannot be cancelled by the band-pass filter 10 as in the first embodiment when frequencies of the input signal S_IN and the carrier (compressing signal) injected to suppress its peak power are so close to each other that the frequency bands of the input signal S_IN and the compressing signal overlap or completely coincide with each other. This embodiment is particularly effective when the carrier for compressing the peak power is injected into a multi-carrier signal or CDMA carrier.

FOURTH EMBODIMENT

[0037] Figure 9 illustrates in block form a fourth embodiment of the present invention, in which the arrangement for canceling the compressing signal component in the Fig. 8 embodiment is applied to the Fig. 7 embodiment. Accordingly, this embodiment uses a diode sensor or thermocouple as the peak power detector as is the case with the second embodiment of Fig. 7. This arrangement permits simplification of the configuration of the peak power detector. The control circuit 17 controls the phase value of the variable phase shifter 46 and the amplitude value of the variable amplifier 47V on a stepwise basis until the minimum peak power is detected. The variable amplifier 47V may be replaced with a variable attenuator. The combined signal generator 9 is the same as that used in the third embodiment. Thus, the peak power detector and the low-frequency oscillator can be made simple-structured.

FIFTH EMBODIMENT

[0038] Figure 10 illustrates in block form a fifth embodiment of the present invention. While the Fig. 9 embodiment has been described to use the compressing signal S_PC as the elimination signal S_CC that is applied to the power combiner/distributor 10 serving as the compressing signal canceller, the Fig. 10 embodiment generates the elimination signal S_CC from the output from the peak power detector 43. That is, in this embodiment, based on the phase and amplitude of the input signal detected by the peak detector 43 in the compressing signal generating path 22, the vector for canceling the remaining compressing component is generated by a low-frequency oscillator 95, a frequency converter 96, the variable phase shifter 92 and the variable amplifier. This method facilitates the generation of the signal for canceling the compressing signal. Further, since the combined signal generating path is similar in configuration to the compressing signal generating path, common modules can be used for respective parts in the device configuration.

SIXTH EMBODIMENT

[0039] Figure 11 illustrates in block form a sixth embodiment of the present invention, in which the signal generated by the low-frequency oscillator 44 in the Fig. 5 embodiment is modulated using a specific code. This scheme allows ease in detecting the peak power of the combined signal S_C that is applied to the power amplifier 8. The compressing signal vector by the low-frequency oscillator 44 is prone to undergo amplitude and phase variations under the influence of noise or the like. With a view to increasing the stability of the compressing signal, this embodiment generates a specific code like a PN sequence by a code generator 49 and uses it to modulate the tone signal generated by the low-frequency oscillator 44. The thus modulated signal is provided via the frequency converter 45, the variable phase shifter 46 and the variable amplifier 47 to the power combiner 6, by which it is combined with the output from the linear signal transfer path 21, and the combined output is input to the power amplifier 8. Since this embodiment uses the code-modulated signal as the compressing signal, the frequency converter 445 needs to be set so that the band of the code-modulated signal lies outside the band of the input signal S_IN.

[0040] In the path 23 (composed of the power combiner 6, the level discriminator 15, the peak power detector 16 and the control circuit 17) for monitoring the peak power of the combined signal, the level discriminator 15 observes the peak power and the peak power detector 16 detects controlled variables of the variable phase shifter 46 and the variable amplifier 47V. At this time, the peak power detector 16 demodulates the input signal by the same code as that generated by the code generator 49. This provides increased stability for the compressing signal. The structure that uses, as the compressing signal, the signal modulated by the code generated by the code generator 49 as described above can be applied as well to the Fig. 7 embodiment. It is also applicable to the embodiments of Figs. 8, 9 and 10, in which case the frequency band of the compressing signal may overlap or completely coincide with the frequency band of the input signal.

[0041] In the Fig. 11 embodiment of the arrangement that uses the code-modulated compressing signal S_PC and in the cases where the arrangement is applied to the embodiments of Figs. 8, 9 and 10, the compressing signal component in the output from the power amplifier 8 can be cancelled by the elimination signal S_CC even if the compressing signal S_PC is frequency converted and then combined with the output signal S_D from the linear signal transfer path 21 in the frequency band overlapping with that of the input signal S_IN. For example, when the input signal is a CDMA signal whose frequency band is indicated by S_TI in Fig. 12, the modulation is performed using a code (a spread spectrum code) that has the same frequency band S_SPC as that S_TI. As a result, the compressing signal component in the output from the power amplifier 8 is cancelled in the band-pass filter 10. In practice, the compressing signal component is not completely cancelled but remains in the CDMA signal band as a residual as shown in Fig. 13; however, it can be reduced negligibly small.

[0042] Similarly, in the case where the input signal S_IN is, for example, a multi-carrier signal in the embodiments of Figs. 8, 9 and 10 and a carrier signal as the compressing signal S_PC is injected in the same frequency band as that of the input signal S_IN (that is, combined by the power combiner 6 with the output signal from the linear signal transfer path 21) as depicted in Fig. 14, a canceling carrier signal opposite in phase to the compressing carrier signal is combined by the power combiner/distributor 10 with the output from the power amplifier 8, by which the remaining compressing carrier signal can cancelled down to a low level as depicted in Fig. 15.

[0043] In the case where the compressing carrier signal is injected outside of the frequency band of the input multi-carrier signal as depicted in Fig. 16, too, the compressing signal component (i.e. the compressing carrier component) in the output from the power amplifier 8 can be cancelled to a sufficiently low level, as shown in Fig. 17, by injecting a cancel carrier signal opposite in phase to the compressing carrier signal in the power combiner/distributor 10.

SEVENTH EMBODIMENT

[0044] Figure 18 illustrates a seventh embodiment of the present invention. In the above-described embodiments of Figs. 5 and 7 to 11, the output distributed from the power combiner 6 is monitored and the variable phase shifter 46 and the variable amplifier 47V are controlled so that the peak power does not exceed the threshold value, but instead the low-frequency oscillator 44 may be controlled based on the monitored output. Shown in Fig. 18 is an application of such control to the Fig. 5 embodiment. The compressing signal generator 4 is made up of the level discriminator 41, the peak power detector 42, the low-frequency oscillator 44, the frequency converter 45 and an amplifier 47. The compressing signal S_PC is generated by the compressing signal generator 4 from a signal from the directional coupler 2 having monitored the input signal to the power amplifier 8. The compressing signal S_PC is combined by the power combiner 6 with the output from the linear signal transfer path 21 to reduce the peak power of the input signal to the power amplifier 8.

[0045] The level discriminator 41 observes the amplitude of the input signal to the power amplifier 8. The instantaneous value of the amplitude thus observed is compared with a threshold value preset in the level discriminator 41, and if the instantaneous value is larger than the threshold value, the input signal S_IN is provided to the peak power detector 42.

[0046] The peak power detector 42 performs orthogonal detection of the input signal S_IN fed from the level discriminator 41 to detect the vector (amplitude and phase values) of the input signal. The thus detected amplitude and phase values are set in the low-frequency oscillator 44.

[0047] The low-frequency oscillator 44 is formed by a synthesizer in which the amplitude and phase values can be set. In this instance, the phase value is set nearly 180° out of phase with the input signal so as to suppress the amplifier input. The low-frequency oscillator 44 generates a tone signal that has the preset amplitude and phase values. This provides a vector that suppresses the peak power.

[0048] The output from the low-frequency oscillator 44 is frequency-converted by the frequency converter 45 to a predetermined band. The oscillator output may be frequency-converted to a band identical with or different from that of the amplifier input signal S_PC. The thus frequency-converted compressing signal S_PC is provided via the amplifier for level adjustment use to the power combiner 6, wherein it is combined with the output signal from the delay line 3. The combined output is mostly applied to the power amplifier 8 but partly to the control path 23.

[0049] In the control path 23 the level discriminator 15 discriminates an instantaneous value of the amplitude of the distributed signal and, when the instantaneous amplitude value is larger than a preset threshold value, the peak power detector 16 performs orthogonal detection of the signal. The control circuit 17 uses the orthogonally-detected signal to control the amplitude and phase values of the tone signal, which is generated by the low-frequency oscillator 44, by an adaptive algorithm on a stepwise basis in a manner to reduce the peak power of the amplifier input signal S_C. The control circuit 17 is formed by a microprocessor, and uses a perturbation algorithm, least square estimation algorithm, or the like as the adaptive algorithm.

[0050] Such control of the low-frequency oscillator 44 as described above is equivalent to suppressing the peak value of the amplifier input signal at the time of receiving it in the base band. The control operation in the base band allows control in the operating band broader than the modulation signal bandwidth. This permits simplification of the control circuit configuration. A modulating wave may be used as the compressing signal, in which case the configuration of this embodiment need not be modified and the same results as mentioned above are obtainable as well.

[0051] In the embodiments described above with reference to Figs. 5, 7 to 11 and 18, a signal opposite in phase to the input signal S_IN at the time of detecting its peak power is generated as the compressing signal S_PC and is combined with the input signal S_IN (properly speaking, the output signal S_D from the linear signal transfer path 21). That is, the compressing signal vector may be determined so that the combined vector always has a constant amplitude value smaller than a predetermined value, but the compressing signal needs to have a component 180° out of phase with at least the input signal vector.

[0052] While the embodiments of Figs. 5, 7 to 11 and 18 have been described to detect and reduce the peak power of the input signal to thereby compress the dynamic range of the input signal power, the following embodiments will be described to compress the dynamic range of the input signal power by reducing the PAPR of the input signal.

EIGHTH EMBODIMENT

[0053] Figure 19 illustrates in block form an eighth embodiment of the present invention, in which the amplifier input signal S_IN is distributed by the directional coupler 2 to the linear signal transfer path 21 formed by the delay line 3 and the compressing signal generating path 22 formed by the compressing signal generator 4. The compressing signal generator 4 is formed by a cascade connection of an orthogonal detector 4A, a constant-envelope signal generator 4B, the frequency converter 45, the variable phase shifter 46 and the variable amplifier 47. The orthogonal detector 4A performs orthogonal detection of the input signal to observe its vector (phase and amplitude). The vector thus observed is provided to the constant-envelope signal generator 4B, which reverse the phase of the input signal. As for the amplitude of the input signal, the constant-envelope composing signal generator 4B estimates the combined signal S_C through numerical calculations and sets the amplitude at such a value that the combined signal S_C will have a constant envelope. By this, it is possible to generate a vector that suppresses the PAPR of the input signal.

[0054] The output from the constant-envelope signal generator 4B is frequency-converted by the frequency converter 45 to a predetermined band. In this instance, the output may be frequency-converted to a band identical with or different from that of the amplifier input signal. The frequency-converted compressing signal S_PC is subjected to final adjustments of its amplitude and phase by the variable phase shifter 46 and the variable amplifier 47, thereafter being injected by the power combiner 6 into the amplifier input signal. The variable amplifier 47V may be replaced with a variable attenuator. In the control path 23, the PAPR detector 19 detects the ratio between the peak voltage and average voltage or between the peak power and average power of the signal divided from the power combiner 6, and when the detected ratio is above a preset threshold value, the PAPR detector 19 performs orthogonal detection of the input signal, and the control circuit 17 controls the variable phase shifter 46 and the variable amplifier 47V by an adaptive algorithm on a stepwise basis. That is, the signals S_D and S_PC will be 180° out-of-phase on the IQ plane after orthogonal detection of the signal S_C combined by the power combiner 6, but the vector of this combined signal S_C does not always have a constant-envelope vector. To avoid this, the control circuit 17 monitors the amplitude of the combined signal S_C through the PAPR detector 19, and controls the variable phase shifter 46 and the variable amplifier 47V to adjust the phase and amplitude of the compressing signal S_PC so that the combined signal S_C will have a predetermined amplitude. In other words, the variable amplifier 47V and the variable phase shifter 46 control the amplitude and phase of the constant-envelope composing signal S_PC on a stepwise basis so that the combined signal S_C will have a constant-envelope vector. This control can be provided by various adaptive algorithms such as the steepest descent method and the most likelihood estimation method.

[0055] The PAPR detector 19 can be implemented by a diode sensor, for instance. In the case of measuring the peak power, a diode sensor of a small time constant is used. The sensor output is sampled to detect an instantaneous value of the sensor input voltage, and the maximum instantaneous value is set as the peak power value. In the case of measuring the average power, a diode sensor of a large time constant is used; the sensor output is sampled and the average value is set as the average power. A thermocouple may be used in place of the diode sensor. The control circuit 17 is formed by a microcomputer, and controls the variable phase shifter 46 and the variable amplifier 47V by a perturbation algorithm, least square estimation algorithm, or the like. The variable amplifier 47V may be replaced with a variable attenuator, in which case, too, it is possible to achieve the same PAPR reduction as described above.

[0056] For example, in the case of an input signal with a 10-dB PAPR, a 4-dB suppression of the peak power will provide a 6-dB PAPR reduction of the input combined signal S_C to the power amplifier 8. This permits reduction of a 10-dB output back-off down to 6 dB prior to the suppression of the peak power. The 4-dB suppression of the peak power has such an influence on the amplification efficiency of the power amplifier 8 as described below. Assuming that the amplifier 8 is a class "A" amplifier whose maximum drain efficiency at the saturation output point is 50% and whose output back-off is defined to be the difference between a 1-dB gain compression point and the operating point, the drain efficiency can be improved to about 10% by the application of the present invention, whereas the drain efficiency is 4% or so when the present invention is not used. Thus, even if the peak power is not completely suppressed, the present invention is effective in improving the amplification efficiency of the power amplifier 8. And this does not ever develop either out-of-band leakage of power or intersymbol interference.

NINTH EMBODIMENT

[0057] Figure 20 illustrates in block form a ninth embodiment of the present invention, which uses an envelope detector 4C in place of the orthogonal detector 4A in the compressing signal generating path 22 in the Fig. 19 embodiment. This permits simplification of the configuration of the compressing signal generator 4.

TENTH EMBODIMENT

[0058] Figure 21 illustrates in block form a tenth embodiment of the present invention. In this embodiment the phase of the compressing signal S_PC is reversed to form the elimination signal S_CC, which is injected into the amplifier output to cancel the PAPR compressing signal at the output side of the amplifier 8. A combined signal generator 100, which constitutes a compressing signal cancellation path, is formed by a cascade connection of a phase invertor signal generator 101, a variable phase shifter 102 and a variable amplifier 103. The variable phase shifter 102 and the variable amplifier 103 are controlled by a control circuit 105 on a step-by-step basis. The control circuit 105 controls the variable phase shifter 102 and the variable amplifier 103 on a stepwise basis until the level of the PAPR compressing signal goes down below a predetermined field intensity.

[0059] The variable amplifier 103 may be substituted with a variable attenuator. This embodiment is suitable for use in the case where frequencies of the input signal S_IN and the carrier injected for PAPR suppression are so close to each other that the injected carrier cannot be cancelled by a band-pass filter or the like as in the eight embodiment. This embodiment is particularly effective, for example, when the carrier for compressing the peak power is injected into a multi-carrier signal or CDMA carrier.

ELEVENTH EMBODIMENT

[0060] Figure 22 illustrates in block form an eleventh embodiment of the present invention, which uses the envelope detector 4C in place of the orthogonal detector 4A in the compressing signal generating path 22 as is the case with the ninth embodiment. This also permits simplification of the compressing signal generator 4. The combined signal generator 100 is identical with that used in the tenth embodiment.

TWELFTH EMBODIMENT

[0061] Figure 23 illustrates in block form a twelfth embodiment of the present invention, which uses the output from the constant-envelope signal generator 4B in the compressing signal generating path 22 to generate the vector for canceling the compressing signal component in the output from the power amplifier 8. This scheme allows ease in the generation of the elimination signal S_CC for canceling the compressing signal S_PC. Further, since the combined signal generating path is similar in configuration to the compressing signal generating path, common modules can be used for respective parts in the device configuration.

[0062] The signal power dynamic range compressing circuits in Figs. 5 and 7 to 11 and in Figs. 19 to 23 are similar in configuration and in effect. Any of the circuits suppresses the peak power or peak-to-average-power ratio to reduce the output back-off of the power amplifier, enabling it to perform high-efficiency amplification.

THIRTEENTH EMBODIMENT

[0063] Figure 24 illustrates in block form a thirteenth embodiment of the present invention, in which the compressing signal generator 4 is made up of the orthogonal detector 4A, the constant-envelope signal generator 4B, the frequency converter 45 and the amplifier 47.

[0064] The orthogonal detector 4A performs orthogonal detection of the input signal S_IN to observe its vector (amplitude and phase values). The vector thus observed is set by the constant-element signal generator 4B to be nearly 180° out of phase with the amplifier input signal S_IN so as to suppress it. The output from the constant-envelope signal generator 4B is frequency-converted by the frequency converter 45 to a predetermined band. In this instance, the output may be frequency-converted to a identical band with or different band from that of the input signal of amplifier. The frequency-converted compressing signal S_PC is adjusted in level by the amplifier 47, and combined by the power combiner 6 with the signal S_D from the delay line 3, and the combined signal S_C is provided to the amplifier 8.

[0065] The control path 23 comprises the PAPR detector 19 and the control circuit 17. The PAPR detector 19 detects the peak power and average power of the combined signal distributed from the power combiner 6 and, when the PAPR is above a present threshold value, performs orthogonal detection of the combined signal to obtain its phase and amplitude. Based on the thus detected phase and amplitude, the control circuit 17 controls the amplitude and phase values of the constant-envelope signal generator 4B on a stepwise basis so that the PAPR goes down below the threshold value. The control circuit 17 is formed by a microprocessor, and uses a perturbation algorithm, least square estimation algorithm, or the like.

[0066] The control circuit 17 further controls the amplitude and phase values of the constant-envelope signal generator 4B in a manner to reduce the PAPR of the input signal to the amplifier 8 (which is the combined signal of the outputs from the linear signal transfer path 21 formed by the delay line 3 and the compressing signal generating path 22). The control of the constant-envelope signal generator 4B is equivalent to the suppression of the PAPR at the time of receiving the amplifier input signal S_IN in the base band. The control operation in the base band allows control in the operating band broader than the modulation signal bandwidth. This permits simplification of the control circuit configuration. A tone signal may be used as the compressing signal, in which case the configuration of this embodiment need not be modified and the same results as mentioned above are obtainable as well.

[0067] While in the above the present invention has been described as being applied to the compression of the power dynamic range of the input signal to the power amplifier 8, the invention is not limited specifically thereto. By applying the invention to, for instance, the input of an A/D converter, its input range can be reduced through the compression of the power dynamic range of input signal thereto-this makes it possible to use an A/D converter that is simple-structured accordingly and hence is inexpensive

EFFECT OF THE INVENTION

[0068] As described above, the signal power dynamic range compressing circuit according to the present invention does not clip the input signal, but instead generates a compressing signal based on the input signal and combines it with the input signal having passed through a linear signal transfer path to thereby compress the signal power dynamic range, and hence develops no out-of-band leakage of power. Further, since the phase of the compressing signal is set in accordance with the input signal, the compression of the signal power dynamic range can effectively achieve even in the case where the input signal is a modulated signal and its phase varies.

[0069] In the power amplifying circuit having a power amplifier connected to the output side of the signal power dynamic range compressing circuit, the provision compressing signal cancel means at the output side of the power amplifier makes it possible to achieve high-efficiency amplification that is completed within the transmitting side, without exerting the influence of the compressing signal on the receiving side.

Claims

1. A signal power dynamic range compressing circuit comprising:

a directional coupler (2) for distributing an input signal to two paths;

a linear signal transfer path (21) over which one of the distributed input signals is linearly transferred;

a compressing signal generating path (22) including a compressing signal generating part (4) for generating, based on the other distributed input signal, a compressing signal containing a component opposite in phase to the other distributed input signal; and

a power combiner (6) for power-combining output signals from said linear signal transfer path (21) and said compressing signal generating path (22);

characterized in that:

said compressing signal is always combined with the output from said linear signal transfer path; and

there is further provided a compressing signal adjustment part (11) responsive to said combined signal, for controlling the compressing signal so that the peak power of said combined signal distributed from said power combiner (6) goes down below a preset value.

2. The compressing circuit of claim 1, wherein said compressing signal generating part (4) comprises:

a level discriminator (41) for detecting the peak power of said input signal above a predetermined level;

a peak power detector (42) responsive to the detection of said peak power to detect the phase of said input signal;

a low-frequency oscillator (44) for generating a low-frequency signal nearly 180° out of phase with said detected phase; and

a frequency converter (45) for converting said low-frequency signal to a desired frequency band and for outputting said frequency-converted signal as said compressing signal.

3. The compressing circuit of claim 1, wherein said compressing signal generating part (4) comprises:

a level discriminator (41) for detecting the peak power of said input signal above a predetermined level;

a peak power detector (43) responsive to the detection of said peak power to detect the amplitude of said input signal;

a low-frequency oscillator (44) having set therein said detected amplitude, for generating a low-frequency signal nearly 180° out of phase with the phase of said input signal; and

a frequency converter (45) for converting said low-frequency signal to a desired frequency band and for outputting said frequency-converted signal as said compressing signal.

4. The compressing circuit of claim 1, wherein said compressing signal generating part (4) comprises:

a level discriminator (41) for detecting the peak power of said input signal above a predetermined level;

a peak power detector (42) responsive to the detection of said peak power to detect the phase and amplitude of said input signal;

a low-frequency oscillator (44) for generating a low-frequency signal nearly 180° out of phase with said detected phase of said input signal;

modulating signal generating means (49) for generating a predetermined modulating signal;

a modulation circuit (48) for modulating said low-frequency signal by said modulating signal to generate a modulated low-frequency signal; and

a frequency converter (45) for converting said modulated low-frequency signal to a desired frequency band and for outputting said frequency-converted signal as said compressing signal.

5. The compressing circuit of claim 4, wherein said modulating signal generating means (49) is a code generator for generating a code of a specific pattern as said modulating signal.

6. The compressing circuit of any one of claims 1 to 4, wherein said compressing signal generating part (4) comprises a variable phase shifter (46) for adjusting the phase of said compressing signal and variable amplitude means (47V) for adjusting the amplitude of said compressing signal, and wherein said compressing signal adjustment part (11) is adapted to control said variable phase shifter (46) and said variable amplitude means (47V) so that the peak power of said combined signal distributed from said power combiner goes down below a preset value.

7. The compressing circuit of claim 6, wherein said compressing signal adjustment part (11) comprises: combined signal level discriminating means (15) for discriminating the level of said distributed combined signal above a preset value; a combined signal peak power detector (16) responsive to the detection of said signal level above said preset value to detect the phase and amplitude of said combined signal; and a control circuit (17) for controlling said variable phase shifter (46) and said variable amplitude means (47V) based on said detected phase and amplitude of said combined signal so that the level of said combined signal goes down to below said predetermined value.

8. The compressing circuit of claim 1, wherein said compressing signal generating part (4) comprises:

an orthogonal detector (4A) for performing orthogonal detection of said input signal and for outputting the phase and amplitude of said input signal;

a constant-envelope composing signal generator (48) for inverting said detected phase of said input signal to generate an inverted-phase signal; and

a frequency converter (45) for converting said inverted phase signal to a desired frequency band and for outputting said frequency-converted signal as said compressing signal.

9. The compressing circuit of claim 1, wherein said compressing signal generating part (4) comprises:

an envelope detector (4C) for detecting the envelope of said input signal and for outputting the phase and amplitude of said input signal;

a constant-envelope composing signal generator (4B) for inverting said detected phase of said input signal to generate an inverted-phase signal; and

a frequency converter (45) for converting said inverted phase signal to a desired frequency band and for outputting said frequency-converted signal as said compressing signal.

10. The compressing circuit of claim 8 or 9, wherein said compressing signal generating part (4) comprises a variable phase shifter (46) for adjusting the phase of said compressing signal and variable amplitude means (47V) for adjusting the amplitude of said compressing signal, and the compressing circuit further comprises a compressing signal adjustment part (11) for controlling said variable phase shifter (46) and said variable amplitude means (47V) so that the peak power of said combined signal distributed from said power combiner goes down below a preset value.

11. The compressing circuit of claim 10, wherein said compressing signal adjustment part (11) comprises: power ratio detecting means (19) for detecting the peak-to-average-power ratio of said distributed combined signal above a preset value; and a control circuit (17) responsive to the detection of said power ratio of said combined signal above said preset value to control said variable phase shifter (46) and said variable amplitude means (47V) so that said power ratio goes down below said preset value.

12. The compressing circuit of claim 2 or 3, further comprising a compressing signal adjustment part (11) for controlling said low-frequency oscillator (44) so that the peak power of said combined signal distributed from said power distributor goes down below a preset value.

13. The compressing circuit of claim 12, wherein said compressing signal adjustment part (11) comprises: combined signal level discriminating means (15) for discriminating the level of said distributed combined signal above a preset value; a combined signal peak power detector (16) responsive to the detection of said signal level above said preset value to detect the phase and amplitude of said combined signal; and a control circuit (17) for controlling said low-frequency oscillator (44) based on said detected phase and amplitude of said combined signal so that the level of said combined signal goes down to below said predetermined value.

14. The compressing circuit of claim 6, wherein said compressing signal adjustment part (11) comprises: peak-to-average-power ratio detecting means (19) for detecting the peak-to-average-power ratio of said distributed combined signal above a preset value; and a control circuit (17) responsive to the detection of said peak-to-average-power ratio of said combined signal above said preset value to control said variable phase shifter (46) and said variable amplitude means (47V) so that said detected peak-to-average-power ratio goes down below said preset value.

15. The compressing circuit of any one of claims 2, 3, and 4, wherein said frequency converter (45) frequency-converts said low-frequency signal to a frequency band different from that of said input signal.

16. The compressing circuit of any one of claims 2, 3, and 4, wherein said frequency converter (45) frequency-converts said low-frequency signal to the same frequency band as that of said input signal.

17. A power amplifying circuit which comprises said compressing circuit of any one of claims 2, 3, 4, 8 and 9 and a power amplifier (8) connected to the output of said power combiner (6).

18. The power amplifying circuit of claim 17, which further comprises compressing signal cancel means (10) connected to the output side of said power amplifier (8) for canceling said compressing signal.

19. The power amplifying circuit of claim 18, wherein said compressing signal cancel means (10) is a filter.

20. The power amplifying circuit of claim 18, wherein said compressing signal cancel means (10) comprises: a directional coupler (18) inserted between said compressing signal generating part (4) and said power combiner (6), for providing said compressing signal to said power combiner connected to one output terminal of said directional coupler (18) itself and for distributing said compressing signal to the other output terminal; a cancel signal generator (9) for generating, based on said compressing signal fed from said other output terminal of said directional coupler (18), a cancel signal nearly 180° out of phase with said compressing signal; and a power combiner/distributor (12) for combining said cancel signal and the output from said power amplifier (8) to provide the output from said power amplifying circuit.

21. The power amplifying circuit of claim 20, wherein said cancel signal generator (9) comprises a phase inverter (91) for inverting the phase of said distributed compressing signal, a variable phase shifter (92) for adjusting the phase value of said phase-inverted compressing signal, and variable amplitude means (93) for adjusting the amplitude of said phase-adjusted compressing signal and for applying said amplitude-adjusted compressing signal to said power combiner/distributor (12), said power amplifying circuit further comprising a cancel signal control circuit (50) for detecting the peak power of the output signal from said power amplifying circuit distributed by said power combiner/distributor (12) to detect the phase and amplitude of said distributed output signal at that time and for controlling said variable phase shifter (92) and said variable amplitude means (93) based on said detected phase and amplitude.

22. The power amplifying circuit of claim 20, wherein said cancel signal generator (9) comprises a phase inverter (91) for inverting the phase of said distributed compressing signal, a variable phase shifter (92) for adjusting the phase value of said phase-inverted compressing signal, and variable amplitude means (93) for adjusting the amplitude of said phase-adjusted compressing signal and for applying said amplitude-adjusted compressing signal to said power combiner/distributor (12), said power amplifying circuit further comprising a cancel signal control circuit (50) for detecting the peak-to-average-power ratio of the output signal from said power amplifying circuit distributed by said power combiner/distributor (12) and for controlling said variable phase shifter (92) and said variable amplitude means (93) so that said detected value of said peak-to-average-power ratio does not exceed a predetermined value.

Ansprüche

1. Signalleistungs-Dynamikbereichs-Kompressionsschaltung mit:

einem Richtkoppler (2) zum Verteilen eines Eingangssignals auf zwei Pfade;

einem linearen Signalübertragungspfad (21), auf dem eines der verteilten Eingangssignale linear übertragen wird;

einem Kompressionssignalerzeugungspfad (22), der ein Kompressionssignalerzeugungsteil (4) umfasst, zum Erzeugen, basierend auf dem anderen verteilten Eingangssignal, eines Kompressionssignals, das eine Komponente von zu dem anderen verteilten Eingangssignal entgegengesetzter Phase hat; und

einem Leistunskombinierer (6) zum Leistungskombinieren von Ausgangssignalen des linearen Übertragungspfades (21) und des Kompressionssignalerzeugungspfades (22);

dadurch gekennzeichnet, dass:

das Kompressionssignal immer mit der Ausgabe des linearen Signalübertragungspfades kombiniert wird; und

ferner ein Kompressionssignal-Einstellteil (11) vorgesehen ist, das auf das kombinierte Signal reagiert, zum Steuern des Kompressionssignals derart, dass die Spitzenleistung des aus dem Leistungskombinierer (6) verteilten kombinierten Signals unter einen voreingestellten Wert abfällt.

2. Kompressionsschaltung nach Anspruch 1, bei der das Kompressionssignalerzeugungsteil (4) umfasst:

einen Pegeldiskriminator (41) zum Erfassen der Spitzenleistung des Eingangssignals oberhalb eines vorgegebenen Pegels;

einen Spitzenleistungsdetektor (42), der auf die Erfassung der Spitzenleistung reagiert, um die Phase des Eingangssignals zu erfassen;

einen Niederfrequenzoszillator (44) zum Erzeugen eines Niederfrequenzsignals nahezu 180° außer Phase zu der erfassten Phase; und

einen Frequenzwandler (45) zum Wandeln des Niederfrequenzsignals in ein gewünschtes Frequenzband und zum Ausgeben des frequenzgewandelten Signals als das Kompressionssignal.

3. Kompressionsschaltung nach Anspruch 1, bei der das Kompressionssignalerzeugungsteil (4) umfasst:

einen Pegeldiskriminator (41) zum Erfassen der Spitzenleistung des Eingangssignals oberhalb eines vorgegebenen Pegels;

einen Spitzenleistungsdetektor (43), der auf die Erfassung der Spitzenleistung reagiert, um die Amplitude des Eingangssignals zu erfassen;

einen Niederfrequenzoszillator (44), in dem die erfasste Amplitude eingestellt ist, um ein Niederfrequenzsignal nahezu 180° außer Phase zu der Phase des Eingangssignals zu erzeugen; und

einen Frequenzwandler (45) zum Wandeln des Niederfrequenzsignals in ein gewünschtes Frequenzband und zum Ausgeben des frequenzgewandelten Signals als das Kompressionssignal.

4. Kompressionsschaltung nach Anspruch 1, bei der das Kompressionssignalerzeugungsteil umfasst:

einen Pegeldiskriminator (41) zum Erfassen der Spitzenleistung des Eingangssignals oberhalb eines vorgegebenen Pegels;

einen Spitzenleistungsdetektor (42), der auf die Erfassung der Spitzenleistung reagiert, um die Phase und Amplitude des Eingangssignals zu erfassen;

einen Niederfrequenzoszillator (44) zum Erzeugen eines Niederfrequenzsignals nahezu 180° außer Phase zu der erfassten Phase des Eingangssignals;

Modulationssignalerzeugungsmittel (49) zum Erzeugen eines vorgegebenen Modulationssignals;

eine Modulationsschaltung (48) zum Modulieren des Niederfrequenzsignals mit dem Modulationssignal, um ein moduliertes Niederfrequenzsignal zu erzeugen; und

einen Frequenzwandler (45) zum Wandeln des modulierten Niederfrequenzsignals in ein gewünschtes Frequenzband und zum Ausgeben des frequenzgewandelten Signals als das Kompressionssignal.

5. Kompressionsschaltung nach Anspruch 4, bei der das Modulationssignalerzeugungsmittel (49) ein Code-Generator zum Erzeugen eines Codes mit einem spezifischen Muster als das Modulationssignal ist.

6. Kompressionsschaltung nach einem der Ansprüche 1 bis 4, bei der das Kompressionssignalerzeugungsteil (4) einen variablen Phasenschieber (46) zum Einstellen der Phase des Kompressionssignals und variable Amplitudenmittel (47V) zum Einstellen der Amplitude des Kompressionssignals umfasst, und wobei das Kompressionssignal-Einstellteil (11) eingerichtet ist, den variablen Phasenschieber (46) und das variable Amplitudenmittel (47V) so zu steuern, dass die Spitzenleistung des von dem Leistungskombinierer verteilten kombinierten Signals unter einen voreingestellten Wert abfällt.

7. Kompressionsschaltung nach Anspruch 6, bei der das Kompressionssignal-Einstellteil (11) umfasst: Kombinationssignal-Pegeldiskriminationsmittel (15) zum Diskriminieren des Pegels des verteilten kombinierten Signals oberhalb eines voreingestellten Wertes;
einen Kombinationssignal-Spitzenleistungsdetektor (16), der auf die Erfassung des Signalpegels oberhalb des voreingestellten Wertes reagiert, um Phase und Amplitude des kombinierten Signals zu erfassen; und
eine Steuerschaltung (17) zum Steuern des variablen Phasenschiebers (46) und des variablen Amplitudenmittels (47V) basierend auf der erfassten Phase und Amplitude des kombinierten Signals, so dass der Pegel des kombinierten Signals unter den vorgegebenen Wert fällt.

8. Kompressionsschaltung nach Anspruch 1, bei der das Kompressionssignalerzeugungsteil (4) umfasst:

einen orthogonalen Detektor (4A) zum Durchführen von orthogonaler Erfassung des Eingangssignals und zum Ausgeben der Phase und Amplitude des Eingangssignals;

einen Konstanthüllkurven-Zusammensetzungssignalgenerator (4B) zum Invertieren der erfassten Phase des Eingangssignals, um ein phaseninvertiertes Signal zu erzeugen; und

einen Frequenzwandler (45) zum Wandeln des phaseninvertierten Signals in ein gewünschtes Frequenzband und zum Ausgeben des frequenzgewandelten Signals als das Kompressionssignal.

9. Kompressionsschaltung nach Anspruch 1, bei der das Kompressionssignalerzeugungsteil (4) umfasst:

einen Hüllkurvendetektor (4C) zum Erfassen der Hüllkurve des Eingangssignals und zum Ausgeben der Phase und Amplitude des Eingangssignals;

einen Konstanthüllkurven-Zusammensetzungssignalgenerator (4B) zum Invertieren der erfassten Phase des Eingangssignals, um ein phaseninvertiertes Signal zu erzeugen; und

einen Frequenzwandler (45) zum Wandeln des phaseninvertierten Signals in ein gewünschtes Frequenzband und zum Ausgeben des frequenzgewandelten Signals als das Kompressionssignal.

10. Kompressionsschaltung nach Anspruch 8 oder 9, bei der das Kompressionssignalerzeugungsteil (4) einen variablen Phasenschieber (46) zum Einstellen der Phase des Kompressionssignals und variable Amplitudenmittel (47V) zum Einstellen der Amplitude des Kompressionssignals umfasst und die Kompressionsschaltung ferner ein Kompressionssignal-Einstellteil (11) zum Steuern des variablen Phasenschiebers (46) und der variablen Amplitudenmittel (47V) derart, dass die Spitzenleistung des von dem Leistungskombinierer verteilten kombinierten Signals unter einen vorgegebenen Wert fällt, umfasst.

11. Kompressionsschaltung nach Anspruch 10, bei der das Kompressionssignal-Einstellteil (11) umfasst: Leistungsverhältniserfassungsmittel (19) zum Erfassen des Spitze-/Durchschnitt-Leistungsverhältnisses des verteilten kombinierten Signals oberhalb eines vorgegebenen Wertes; und eine Steuerschaltung (17), die auf die Erfassung des Leistungsverhältnisses des kombinierten Signals oberhalb des voreingestellten Wertes reagiert, um den variablen Phasenschieber (46) und die variablen Amplitudenmittel (47V) so zu steuern, dass das Leistungsverhältnis unter den vorgegebenen Wert fällt.

12. Kompressionsschaltung nach Anspruch 2 oder 3, ferner mit einem Kompressionssignal-Einstellteil (11) zum Steuern des Niederfrequenzoszillators (44) derart, dass die Spitzenleistung des von dem Leistungsverteiler verteilten kombinierten Signals unter einen vorgegebenen Wert fällt.

13. Kompressionsschaltung nach Anspruch 12, bei der das Kompressionssignal-Einstellteil (11) umfasst: Kombinationssignal-Pegeldiskriminationsmittel (15) zum Diskriminieren des Pegels des verteilten kombinierten Signals oberhalb eines vorgegebenen Wertes; einen Kombinationssignal-Spitzenleistungsdetektor (16), der auf die Erfassung des Signalpegels oberhalb des vorgegebenen Wertes reagiert, um die Phase und Amplitude des kombinierten Signals zu erfassen; und eine Steuerschaltung (17) zum Steuern des Niederfrequenzoszillators (44) basierend auf der erfassten Phase und Amplitude des kombinierten Signals, so dass der Pegel des kombinierten Signals unter den vorgegebenen Wert fällt.

14. Kompressionsschaltung nach Anspruch 6, bei der das Kompressionssignal-Einstellteil (11) umfasst: Spitzen-/Durchschnittsleistungsverhältniserfassungsmittel (19) zum Erfassen des Spitzen-/Durchschnittsleistungsverhältnisses des verteilten kombinierten Signals oberhalb eines vorgegebenen Wertes und eine Steuerschaltung (17), die auf die Erfassung des Spitze-/Durchschnittsleistungsverhältnisses des kombinierten Signals oberhalb des vorgegebenen Wertes reagiert, um den variablen Phasenschieber (46) und die variablen Amplitudenmittel (47V) so zu steuern, dass das erfasste Spitzen-/Durchschnittsleistungsverhältnis unter den vorgegebenen Wert fällt.

15. Kompressionsschaltung nach einem der Ansprüche 2, 3 und 4, bei der der Frequenzwandler (45) das Niederfrequenzsignal in ein Frequenzband frequenzwandelt, das von demjenigen des Eingangssignals verschieden ist.

16. Kompressionsschaltung nach einem der Ansprüche 2, 3 und 4, bei der der Frequenzwandler (45) das Niederfrequenzsignal in das gleiche Frequenzband wie dasjenige des Eingangssignals wandelt.

17. Leistungsverstärkungsschaltung, die die Kompressionsschaltung nach einem der Ansprüche 2, 3, 4, 8 und 9 und einen mit dem Ausgang des Leistungskombinierers (6) verbundenen Leistungsverstärker (8) umfasst.

18. Leistungsverstärkungsschaltung nach Anspruch 17, die ferner Kompressionssignalauslöschungsmittel (10) umfasst, die an die Ausgangsseite des Leistungsverstärkers (8) angeschlossen sind, um das Kompressionssignal auslöschen.

19. Leistungsverstärkungsschaltung nach Anspruch 18, bei der das Kompressionssignalauslöschungsmittel (10) ein Filter ist.

20. Leistungsverstärkungsschaltung nach Anspruch 18, bei der das Kompressionssignalauslöschungsmittel (10) umfasst: einen zwischen das Kompressionssignalerzeugungsteil (4) und den Leistungskombinierer (6) eingefügten Richtkoppler (18) zum Liefern des Kompressionssignals an den mit einem Ausgangsanschluss des Richtkopplers (18) selbst verbundenen Leistungskombinierer und zum Verteilen des Kompressionssignals an den anderen Ausgangsanschluss; einen Auslöschungssignalgenerator (9) zum Erzeugen, basierend auf dem von dem anderen Ausgangsanschluss des Richtkopplers (18) zugeführten Kornpressionssignal, eines Auslöschungssignals nahezu 180° außer Phase zu dem Kompressionssignal; und einen Leistungskombinierer/Verteiler (12) zum Kombinieren des Auslöschungssignals und der Ausgabe des Leistungsverstärkers (8), um die Ausgabe der Leistungsverstärkungsschaltung zu liefern.

21. Leistungsverstärkungsschaltung nach Anspruch 20, bei der der Auslöschungssignalgenerator (9) einen Phaseninverter (91) zum Invertieren der Phase des verteilten Kompressionssignals, einen variablen Phasenschieber (92) zum Einstellen des Phasenwertes des phaseninvertierten Kompressionssignals und variable Amplitudenmittel (93) zum Einstellen der Amplitude des phaseneingestellten Kompressionssignals und zum Anlegen des amplitudeneingestellten Kompressionssignals an den Leistungskombinierer/Verteiler (12) umfasst, wobei die Leistungsverstärkungsschaltung ferner eine Auslöschungssignalsteuerschaltung (50) zum Erfassen der Spitzenleistung des von dem Leistungskombinierer/Verteiler (12) verteilten Ausgangssignals der Leistungsverstärkungsschaltung umfasst, um die Phase und Amplitude des verteilten Ausgangssignals zu dieser Zeit zu erfassen und den variablen Phasenschieber (92) und das variable Amplitudenmittel (93) basierend auf der erfassten Phase und Amplitude zu steuern.

22. Leistungsverstärkungsschaltung nach Anspruch 20, bei der der Auslöschungssignalgenerator (9) einen Phaseninverter (91) zum Invertieren der Phase des verteilten Kompressionssignals, einen variablen Phasenschieber (92) zum Einstellen des Phasenwertes des phaseninvertierten Kompressionssignals und variable Amplitudenmittel (93) zum Einstellen der Amplitude des phaseneingestellten Kompressionssignals und zum Anlegen des amplitudeneingestellten Kompressionssignals an den LeistungskombiniererNerteiler (12) umfasst und die Leistungsverstärkungsschaltung ferner eine Auslöschungssignalsteuerschaltung (50) zum Erfassen des Spitzen-/Durchschnittsleistungsverhältnisses des Ausgangssignals des von dem Leistungskombinierer/Verteiler (12) verteilten Ausgangssignals der Leistungsverstärkungsschaltung und zum Steuern des variablen Phasenschiebers (92) und der variablen Amplitudenmittel (93) derart, dass der erfasste Wert des Spitzen-/Durchschnittsleistungsverhältnis einen vorgegebenen Wert nicht überschreitet, umfasst.

Revendications

1. Circuit de compression de plage dynamique de puissance de signal comprenant :

un coupleur (2) directionnel destiné à distribuer un signal d'entrée vers deux trajets ;

un trajet (21) de transfert de signal linéaire sur lequel l'un des signaux d'entrée distribués est transféré linéairement ;

un trajet (22) de production de signal de compression comportant un partie (4) de production de signal de compression pour produire, sur la base de l'autre signal d'entrée distribué, un signal de compression contenant une composante qui est en opposition de phase avec l'autre signal d'entrée distribué ; et

un groupeur (6) de puissance destiné à combiner en puissance des signaux de sortie à partir dudit trajet (21) de transfert de signal linéaire et dudit trajet (22) de production de signal de compression ;

caractérisé en ce que :

ledit signal de compression est toujours combiné avec la sortie en provenance dudit trajet de transfert de signal linéaire ; et

on fournit de plus une partie (11) d'ajustement de signal de compression qui est réactif audit signal combiné, pour commander le signal de compression de sorte que la puissance de crête dudit signal combiné distribué à partir dudit groupeur (6) de puissance descende en dessous d'une valeur préétablie.

2. Circuit de compression selon la revendication 1, dans lequel la partie (4) de production de signal de compression comporte :

un discriminateur (41) de niveau destiné à détecter la puissance de crête dudit signal d'entrée au-dessus d'un niveau prédéterminé ;

un détecteur (42) de puissance de crête qui est réactif à la détection de ladite puissance de crête pour détecter la phase dudit signal d'entrée ;

un oscillateur (44) de basse fréquence destiné à produire un signal de basse fréquence qui est en discordance de phase d'environ 180° avec ladite phase détectée ; et

un convertisseur (45) de fréquence destiné à convertir ledit signal de basse fréquence en une bande de fréquence souhaitée et à fournir en sortie le signal converti en fréquence comme étant ledit signal de compression.

3. Circuit de compression selon la revendication 1, dans lequel la partie (4) de production de signal de compression comporte : un discriminateur (41) de niveau destiné à détecter la puissance de crête dudit signal d'entrée au-dessus d'un niveau prédéterminé ;
un détecteur (43) de puissance de crête qui est réactif à la détection de ladite puissance de crête pour détecter l'amplitude dudit signal d'entrée ;
un oscillateur (44) de basse fréquence y ayant établi ladite amplitude détectée, pour produire un signal de basse fréquence qui est en discordance de phase d'environ 180° avec la phase dudit signal d'entrée ; et
un convertisseur (45) de fréquence destiné à convertir ledit signal de basse fréquence en une bande de fréquence souhaitée et à fournir en sortie le signal converti en fréquence comme étant ledit signal de compression.

4. Circuit de compression selon la revendication 1, dans lequel la partie (4) de production de signal de compression comporte :

un discriminateur (41) de niveau destiné à détecter la puissance de crête dudit signal d'entrée au-dessus d'un niveau prédéterminé ;

un détecteur (42) de puissance de crête qui est réactif à la détection de ladite puissance de crête pour détecter la phase et l'amplitude dudit signal d'entrée ;

un oscillateur (44) de basse fréquence destiné à produire un signal de basse fréquence qui est en discordance de phase d'environ 180° avec ladite phase détectée dudit signal d'entrée ;

un moyen (49) de production de signal de modulation servant à produire un signal de modulation prédéterminé ;

un circuit (48) de modulation destiné à moduler ledit signal de basse fréquence par ledit signal de modulation pour produire un signal de basse fréquence modulé ; et

un convertisseur (45) de fréquence destiné à convertir le signal de basse fréquence modulé en une bande de fréquence souhaitée et à fournir en sortie le signal converti en fréquence comme étant ledit signal de compression.

5. Circuit de compression selon la revendication 4, dans lequel le moyen (49) de production de signal de modulation est un générateur de code servant à produire un code d'un motif spécifique comme étant ledit signal de modulation.

6. Circuit de compression selon l'une quelconque des revendications 1 à 4, dans lequel la partie (4) de production de signal de compression comporte un déphaseur (46) variable servant à ajuster la phase dudit signal de compression ainsi qu'un moyen (47V) d'amplitude variable servant à ajuster l'amplitude dudit signal de compression, et dans lequel la partie (11) d'ajustement de signal de compression est adaptée pour commander ledit déphaseur (46) variable et ledit moyen (47V) d'amplitude variable de sorte que la puissance de crête dudit signal combiné distribué à partir dudit groupeur de puissance descende en dessous d'une valeur préétablie.

7. Circuit de compression selon la revendication 6, dans lequel la partie (11) d'ajustement de signal de compression comporte : un moyen (15) de discrimination de niveau de signal combiné servant à différencier le niveau dudit signal combiné distribué au-dessus d'une valeur préétablie ; un détecteur (16) de puissance de crête de signal combiné qui est réactif à la détection dudit niveau de signal au-dessus de ladite valeur préétablie pour détecter la phase et l'amplitude dudit signal combiné ; et un circuit (17) de commande destiné à commander ledit déphaseur (46) variable et ledit moyen (47V) d'amplitude variable sur la base desdites phase et amplitude détectées dudit signal combiné de sorte que le niveau dudit signal combiné descende en dessous de ladite valeur prédéterminée.

8. Circuit de compression selon la revendication 1, dans lequel la partie (4) de production de signal de compression comporte :

un détecteur (4A) orthogonal destiné à effectuer une détection orthogonale dudit signal d'entrée et à fournir en sortie la phase et l'amplitude dudit signal d'entrée ;

un générateur (4B) de signal composant une enveloppe constante destiné à inverser la phase détectée dudit signal d'entrée pour produire un signal à phase inversée ; et

un convertisseur (45) de fréquence destiné à convertir le signal à phase inversée en une bande de fréquence souhaitée et à fournir en sortie le signal converti en fréquence comme étant ledit signal de compression.

9. Circuit de compression selon la revendication 1, dans lequel la partie (4) de production de signal de compression comporte :

un détecteur (4C) d'enveloppe destiné à détecter l'enveloppe dudit signal d'entrée et à fournir en sortie la phase et l'amplitude dudit signal d'entrée ;

un générateur (4B) de signal composant une enveloppe constante destiné à inverser la phase détectée dudit signal d'entrée pour produire un signal à phase inversée ; et

un convertisseur (45) de fréquence destiné à convertir le signal à phase inversée en une bande de fréquence souhaitée et à fournir en sortie le signal converti en fréquence comme étant ledit signal de compression.

10. Circuit de compression selon la revendication 8 ou 9, dans lequel la partie (4) de production de signal de compression comporte un déphaseur (46) variable destiné à ajuster la phase dudit signal de compression ainsi qu'un moyen (47V) d'amplitude variable destiné à ajuster l'amplitude dudit signal de compression, et le circuit de compression comporte en outre une partie (11) d'ajustement de signal de compression pour commander ledit déphaseur (46) variable et ledit moyen (47V) d'amplitude variable de sorte que la puissance de crête dudit signal combiné distribué à partir dudit groupeur de puissance descende en dessous d'une valeur préétablie.

11. Circuit de compression selon la revendication 10, dans lequel ladite partie (11) d'ajustement de signal de compression comporte :

un moyen (19) de détection de rapport de puissance servant à détecter le rapport crête/puissance moyenne dudit signal combiné distribué au-dessus d'une valeur préétablie ; et un circuit (17) de commande qui est réactif à la détection dudit rapport de puissance dudit signal combiné au-dessus de ladite valeur préétablie pour commander ledit déphaseur (46) variable et ledit moyen (47V) d'amplitude variable de sorte que ledit rapport de puissance descende en dessous de ladite valeur préétablie.

12. Circuit de compression selon la revendication 2 ou 3, comprenant en outre une partie (11) d'ajustement de signal de compression pour commander ledit oscillateur (44) de basse fréquence de sorte que la puissance de crête dudit signal combiné distribué à partir dudit distributeur de puissance descende en dessous d'une valeur préétablie.

13. Circuit de compression selon la revendication 12, dans lequel ladite partie (11) d'ajustement de signal de compression comporte : un moyen (15) de discrimination de niveau de signal combiné servant à différencier le niveau dudit signal combiné distribué au-dessus d'une valeur préétablie ; un détecteur (16) de puissance de crête de signal combiné qui est réactif à la détection dudit niveau de signal au-dessus de ladite valeur préétablie pour détecter la phase et l'amplitude dudit signal combiné ; et un circuit (17) de commande destiné à commander ledit oscillateur (44) de basse fréquence en se basant sur lesdites phase et amplitude détectées dudit signal combiné de sorte que le niveau dudit signal combiné descende en dessous de ladite valeur prédéterminée.

14. Circuit de compression selon la revendication 6, dans lequel ladite partie (11) d'ajustement de signal de compression comporte : un moyen (19) de détection de rapport crête/puissance moyenne servant à détecter le rapport crête/puissance moyenne dudit signal combiné distribué au-dessus d'une valeur préétablie; et un circuit (17) de commande qui est réactif à la détection dudit rapport crête/puissance moyenne dudit signal combiné au-dessus de ladite valeur préétablie pour commander ledit déphaseur (46) variable et ledit moyen (47V) d'amplitude variable de sorte que ledit rapport crête/puissance moyenne détecté descende en dessous de ladite valeur préétablie.

15. Circuit de compression selon l'une quelconque des revendications 2, 3 et 4, dans lequel le convertisseur (45) de fréquence convertit en fréquence ledit signal de basse fréquence en une bande de fréquence qui est différente de celle dudit signal d'entrée.

16. Circuit de compression selon l'une quelconque des revendications 2, 3 et 4, dans lequel le convertisseur (45) de fréquence convertit en fréquence ledit signal de basse fréquence en la même bande de fréquence que celle dudit signal d'entrée.

17. Circuit d'amplification de puissance qui comporte ledit circuit de compression selon l'une quelconque des revendications 2, 3, 4, 8 et 9 ainsi qu'un amplificateur (8) de puissance relié à la sortie dudit groupeur (6) de puissance.

18. Circuit d'amplification de puissance selon la revendication 17, qui comporte en outre un moyen (10) d'annulation de signal de compression relié au côté de sortie dudit amplificateur (8) de puissance pour annuler le signal de compression.

19. Circuit d'amplification de puissance selon la revendication 18, dans lequel ledit moyen (10) d'annulation de compression de signal est un filtre.

20. Circuit d'amplification de puissance selon la revendication 18, dans lequel ledit moyen (10) d'annulation de compression de signal comporte : un coupleur (18) directionnel inséré entre ladite partie (4) de production de signal de compression et ledit groupeur (6) de puissance, pour fournir ledit signal de compression audit groupeur de puissance relié à une borne de sortie dudit coupleur (18) directionnel lui-même et pour distribuer le signal de compression à l'autre borne de sortie ; un générateur (9) de signal d'annulation destiné à produire, sur la base dudit signal de compression alimenté à partir de ladite autre borne de sortie dudit coupleur (18) directionnel, un signal d'annulation qui est en discordance de phase d'environ 180° avec ledit signal de compression ; et un combinateur/distributeur (12) de puissance destiné à combiner le signal d'annulation et la sortie à partir dudit amplificateur (8) de puissance pour fournir la sortie à partir dudit circuit d'amplification de puissance.

21. Circuit d'amplification de puissance selon la revendication 20, dans lequel le générateur (9) de signal d'annulation comporte un inverseur (91) de phase destiné à inverser la phase dudit signal de compression distribué, un déphaseur (92) variable destiné à ajuster la valeur de phase dudit signal de compression à phase inversée, et un moyen (93) d'amplitude variable destiné à ajuster l'amplitude dudit signal de compression ajusté en phase et à appliquer le signal de compression ajusté en amplitude audit combinateur/distributeur (12) de puissance, ledit circuit d'amplification de puissance comprenant en outre un circuit (50) de commande de signal d'annulation pour détecter la puissance de crête du signal de sortie à partir dudit circuit d'amplification de puissance distribué par ledit combinateur/distributeur (12) de puissance pour détecter la phase et l'amplitude dudit signal de sortie distribué à cet instant et pour commander ledit déphaseur (92) variable et ledit moyen (93) d'amplitude variable en se basant sur lesdites phase et amplitude détectées.

22. Circuit d'amplification de puissance selon la revendication 20, dans lequel le générateur (9) de signal d'annulation comporte un inverseur (91) de phase pour inverser la phase dudit signal de compression distribué, un déphaseur (92) variable pour ajuster la valeur de phase dudit signal de compression à phase inversée ;
et un moyen (93) d'amplitude variable pour ajuster l'amplitude dudit signal de compression ajusté en phase et pour appliquer le signal de compression ajusté en amplitude audit combinateur/distributeur (12) de puissance, ledit circuit d'amplification de puissance comprenant en outre un circuit (50) de commande de signal d'annulation pour détecter le rapport crête/puissance moyenne du signal de sortie à partir dudit circuit d'amplification de puissance distribué par ledit combinateur/distributeur (12) de puissance et pour commander ledit déphaseur (92) variable et ledit moyen (93) d'amplitude variable de sorte que ladite valeur détectée dudit rapport crête/puissance moyenne ne dépasse pas une valeur prédéterminée.

Drawing