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(11) | EP 1 115 198 A3 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | Frequency detector and phase-locked loop circuit including the detector |
| (57) A three-state phase detector (20), including two latches (41,42) and one NAND gate
(43), is provided with two additional latches (50,51). To detect a phase difference
between first and second input clock signals R and V, the phase detector alternates
among three states responsive to a rising edge of the input R or V signal. Each of
the two additional latches (50,51) and an associated latch (41,42) in the phase detector
together constitute one shift register. When the phase detector gets back to its neutral
state, the NAND gate (43) generates a reset signal, thereby resetting all of these
four latches. Two isolated pulse generators (60,61) are further provided. Each of
the pulse generators makes the pulse width of a frequency difference pulse signal,
output from associated one of the additional latches, constant and then outputs the
pulse signal with the constant width. |