(19)
(11) EP 1 119 003 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
12.09.2001 Bulletin 2001/37

(43) Date of publication A2:
25.07.2001 Bulletin 2001/30

(21) Application number: 00309493.5

(22) Date of filing: 27.10.2000
(51) International Patent Classification (IPC)7: G11C 8/00, H03M 7/16, G11C 5/06
(84) Designated Contracting States:
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
Designated Extension States:
AL LT LV MK RO SI

(30) Priority: 10.12.1999 GB 9929372

(71) Applicant: STMicroelectronics Limited
Almondsbury, Bristol BS32 4SQ (GB)

(72) Inventor:
  • Raymond, Paul
    Bristol BS7 8DJ (GB)

(74) Representative: Driver, Virginia Rozanne et al
Page White & Farrer 54 Doughty Street
London WC1N 2LS
London WC1N 2LS (GB)

   


(54) Address decoder optimization


(57) An method of arranging address decoders in an improved manner in an integrated circuit memory is discussed. In the integrated circuit memory the address lines extending from the address circuitry of the integrated circuit memory are connected to address decoders, each word line of the memory being connected to an address decoder. The address decoders are connected to the address lines in a certain combination such that only one f the address lines is connected to adjacent address decoders.
When connected in this manner the average propagation delay of each address line is substantially uniform. By reducing the maximum propagation delay in comparison with previously known arrangements of address decoders the speed at which the memory can be operated is increased.






Search report