Semiconductor memory devices

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(11)

EP 1 137 010 A8

(12)	CORRECTED EUROPEAN PATENT APPLICATION

(48)	Corrigendum issued on:
	30.01.2002 Bulletin 2002/05

(43)	Date of publication:
	26.09.2001 Bulletin 2001/39

(21)	Application number: 01302652.1

(22)	Date of filing: 22.03.2001

(51)	International Patent Classification (IPC)⁷: G11C 11/406, G06F 11/20

(84)	Designated Contracting States:
	AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
	Designated Extension States:
	AL LT LV MK RO SI

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Priority:

24.03.2000 US 536185

(71)	Applicants:
	Infineon Technologies North America Corp. San Jose, CA 95112 (US) International Business Machines Corporation Armonk, NY 10504 (US)

(72)	Inventors:
	Kirihata, Toshiai Poughkeepsie, NY12603 (US) Mitwalsky, Alexander 01109 Dresden (DE)

(74)	Representative: Vigars, Christopher Ian et al
	Haseltine Lake & Co., Imperial House, 15-19 Kingsway London WC2B 6UD London WC2B 6UD (GB)

(54)	Semiconductor memory devices

(57) A method is provided for refreshing memory cells in semiconductor memories. The method includes the steps of providing a semiconductor memory having memory cells and redundancy memory cells in at least one memory array and an associated redundancy memory array, respectively (1002). The memory cells and the redundancy memory cells are independently refreshed, using addresses generated by a row address counter and a redundancy address counter, respectively (1008). The method optionally includes the step of disabling redundancy wordlines coupled to unused redundancy memory cells, using a master fuse signal corresponding to a master fuse of the semiconductor memory (1004).