BACKGROUND OF THE INVENTION
[0001] As electronic devices utilising wireless digital communications techniques become
increasingly prevalent in modern society, the increase in wireless traffic over a
fixed number of allocated frequency bands forces product designers to maximise efficient
allocation and use of the frequency spectrum.
[0002] To achieve more efficient utilisation of a limited frequency spectrum and increased
performance of radio traffic on adjacent channels, designers frequently employ techniques
which involve filtering of the signal at various stages in the transmission process.
However, while filtering the digital signal at the transmitter side of a communications
link improves certain characteristics of the transmitted signal, this practice places
additional burden on the receiver. Specifically, the digital signal recovered by the
receiver demodulator typically is not a clean digital signal - rather, it tends to
be sinusoidal in nature. In order to interface the recovered signal with digital receiver
circuitry, it is necessary to employ a circuit known as a data slicer to square up
the received signal into a format compatible with standard digital logic.
[0003] One type of data slicer known in the art consists primarily of a comparator, which
compares the recovered signal with a reference level. Such prior art data slicers
then effectively square up the input signal by transitioning their output between
logic high and logic low levels as the input signal crosses the reference level.
[0004] However, one disadvantage with many prior art data slicers is that extended sequences
of ones or zeros in the recovered data stream output from the receiver demodulator
can cause erroneous output from the data slicer. These quasi-DC data segments can
cause the reference level to begin drifting, or a coupling capacitor to begin accumulating
a significant charge, thereby degrading the accuracy of the signal presented to the
comparator in the data slicer. Such effects increase the probability of error being
introduced in the demodulated data.
[0005] Certain prior art data slicer designs require each received transmission to begin
with a predetermined preamble bit sequence in order for the data slicer to acquire
the proper reference level. However, such preamble bits either reduce the usable channel
data rate, or increase the channel frequency bandwidth.
[0006] Many modern communications systems incorporate time division duplexing or time division
multiplexing wherein transmit and receive data from one or more devices is communicated
via separate timeslots of a given frequency channel. In such systems, the receiver
demodulator will send out valid data on an intermittent basis.
[0007] Frequency hopping communications techniques are increasingly popular in modern communications
systems due to their improved power efficiency, security, and resistance to interference.
However, varying channel characteristics may result in differing nominal DC levels
in the demodulator output for each channel. Therefore, each channel may have a unique
ideal reference level for the data slicer comparator.
[0008] Communications channel interference, and other effects can cause the received data
to contain errors. A data slicer reference value derived from an error-ridden packet
of received data may also be erroneous.
SUMMARY OF THE INVENTION
[0009] We have appreciated problems and characteristics of the systems discussed above.
In particular, we have appreciated the need to prevent the introduction of errors
due to data slicer reference level drift. We have also appreciated the advantage of
a data slicer configured to operate without requiring a preamble bit sequence and
to prevent the reference level from changing between periods during which valid data
is received. We have also appreciated the advantage of a data slicer configured to
store separate data slicer reference levels for each channel of a multi-channel receiver
and for the data slicer to only update channel reference values only when the data
received is error-free.
[0010] The invention is defined in the claims to which reference is now directed.
[0011] The invention includes a data slicer, and a method for slicing data. An embodiment
of the data slicer compares an input signal to a reference level, outputting a logic
high level when the input signal level is greater than the reference level, and a
logic low level when the input signal level is below the reference level.
[0012] The data slicer generates a reference level based upon the input signal. The reference
level can be determined by applying the input signal to a lowpass filter. After input
data has been applied to the filter for a predetermined time period, the reference
level is sampled by a signal level measurement circuit, which may include an analog-to-digital
converter. The reference level is thereafter held constant at a desired level for
the remainder of the received data frame. The desired level may be the measured level.
Optionally, the desired level may be equal to a lower limit if the measured level
is below the lower limit, or the desired level may be equal to an upper limit if the
measured level is above the upper limit. The reference level may be determined by
the state of a signal generator, which may include a digital-to-analog converter,
that is connected to the comparator by a switch changing from an open to a closed
position.
[0013] The measured reference level is stored so that the filter can be set to it as an
initial condition at the start of subsequent transmissions on the given channel. Optionally,
the reference level might only be stored if the data for which it was used to receive
contained no errors. The reference levels might be stored by a controller, which controller
would also control the analog-to-digital and digital-to-analog converters, and the
state of the switch. The controller may store an independent reference level for each
channel of a multi-channel receiver.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014]
Figure 1 of the drawings is a schematic block diagram of one embodiment of the invention.
Figure 2 of the drawings is a flow chart describing operation of the digital controller
in the embodiment of Figure 1.
Figure 3 of the drawings is a graph of the analog-to-digital converter and digital-to-analog
converter timing.
Figure 4 of the drawings is a graph of a typical data slicer input signal, and the
resulting data slicer output signal.
DETAILED DESCRIPTION OF THE INVENTION
[0015] While this invention is susceptible to embodiment in many different forms, there
are shown in the drawings and will be described in detail herein several specific
embodiments, with the understanding that the present disclosure is to be considered
as an exemplification of the principles of the invention and is not intended to limit
the invention to embodiments illustrated.
[0016] Figure 1 of the drawings illustrates a first embodiment of the present invention.
The data slicer input signal is applied to terminal 30. The input signal will typically
be DC-coupled from a demodulator output (not shown). The input signal is applied directly
to the positive terminal of comparator U1. The input signal is also applied to a lowpass
filter network, comprised of resistor R1 and capacitor Cl. In the preferred embodiment,
the lowpass RC filter has a corner frequency of 400 Hz, and serves to extract the
DC component of the input signal. The RC filter applies the DC component (i.e. the
"reference level") to the negative terminal of comparator U1. Data slicer output 31
is the output of comparator U1. Figure 4 depicts the typical relationship between
a data slicer's input and output signals. Input signal 120 represents a typical input
signal. Reference level 122 is derived from input signal 120. Output signal 121 transitions
each time input signal 120 crosses reference level 122.
[0017] The reference level is also buffered by opamp U2 for sampling by analog-to-digital
converter U3. Digital controller U4 triggers ADC U3, and the sampled value is passed
to controller U4.
[0018] Digital controller U4 can specifically determine the data slicer reference level
applied to comparator U1 by applying a specific reference value to digital-to-analog
converter U5, and closing electronically-operated switch SW1.
[0019] The operation of the data slicer is controlled by digital controller U4, and illustrated
by the flowchart of Figure 2. The embodiment described by Figures 1 and 2 is specifically
adapted to a frequency hopping spread spectrum receiver. However, inasmuch as the
illustrated embodiment could be adapted by one of ordinary skill in the art, the invention
may easily be applied to other types of receivers as well, such as a single-channel
time division duplexed receiver.
[0020] In the illustrated embodiment, microcontroller U4 includes memory registers that
contain a reference level for each channel in a frequency hopping link. Initially,
in step 10, each register contains a default value corresponding to a nominal data
slicer reference level. In step 11, controller U4 programs DAC U5 with the first stored
reference level. Controller U4 then closes switch SW1, thereby applying the reference
level to capacitor C1 and the negative terminal of comparator U1. Capacitor C1 charges
to the reference voltage during step 13, thereby setting the initial condition of
the lowpass filter, until the data slicer begins receiving demodulator output corresponding
to valid received data.
[0021] The data slicer timing is illustrated in the graph of Figure 3. Line 100 depicts
the timing of a receive data frame. Line 101 depicts the timing of both the state
of switch SW1, and the write status of DAC U5. Line 102 depicts the timing of ADC
U3 being triggered to sample the reference level. Controller U4 opens switch SW1,
step 14, at time 110. The filtered demodulator output adjusts the reference level
across C1 between time 110 and time 111. Meanwhile, buffer U2 applies the reference
level to the input of ADC U3. At time 111, U4 causes ADC U3 to sample the reference
voltage, step 15.
[0022] Controller U4 then determines the reference level that will be used for the remainder
of the receive data frame. If the sampled level is greater than a predetermined maximum
reasonable limit, step 16, the sampled value is presumed erroneous and the upper limit
value is written to DAC U5, step 17. If the sampled level is below a predetermined
minimum limit, step 18, then the sampled value is also presumed erroneous and the
minimum limit is written to DAC U5, step 19. Otherwise, the sampled reference level
is written to DAC U5, step 20.
[0023] After the reference level is chosen, it is written to DAC U5 and switch SW1 is closed
at time 112, step 21. The reference value for comparator U1 is then held at the programmed
DAC level throughout the remainder of the receive data frame, from time 112 to time
113. Therefore, even prolonged periods of steady-state demodulator output will not
disturb the optimal data slicer reference level. Upon completion of a frame at time
113, controller U4 detects whether the frame was received without error in step 22.
In the embodiment of Figure 1, an external error detection circuit (not shown), which
is standard and known in the art of digital receivers, signals controller U4 via input
32 when the data was received without error. If the frame was error free, the data
slicer reference value that was used is written to the memory register corresponding
to the current channel, step 23. The stored reference level becomes the initial condition
to which the filter will be set before the next reception on that channel. If the
received data contained errors, the reference level derived from the erroneous transmission
is not stored. Because erroneous reference levels are not stored, a bad transmission
does not corrupt the data slicer reference.
[0024] Finally, controller U4 advances to the next channel in the hopping sequence, and
returns to the first channel in the sequence after the last channel is reached, steps
24-26. The above-described process is repeated for each channel in the hopping sequence.
[0025] The foregoing description and drawings merely explain and illustrate the invention
and the invention is not limited thereto except insofar as the appended claims are
so limited, inasmuch as those skilled in the art, having the present disclosure before
them will be able to make modifications and variations therein without departing from
the scope of the invention. In particular, it is envisioned that one of ordinary skill
in the art could readily implement the above-described invention entirely in the digital
domain by digitising the demodulator output and processing the digital signal using
constructs analogous to those described above.
1. A data slicer for squaring-up a digital input signal recovered by a receiver demodulator,
the data slicer comprising:
• a comparator containing at least a first input terminal to which the input signal
is applied, and a second input terminal to which a reference level is applied;
• a filter to which the input signal is applied, the output of which constitutes the
reference level and is applied to the second terminal of the comparator;
• a signal level measurement circuit for measuring the reference level, the input
of which is connected to the second terminal of the comparator;
• a switch with output connected to the second terminal of the comparator;
• a signal generator having an output connected to the switch input;
• a controller, which controller is connected to the signal level measurement circuit
output, the signal generator, and the switch;
whereby the output of the comparator is the squared-up digital signal, and the controller
can measure and specify the reference level.
2. The data slicer of claim 1, in which the filter is comprised of a lowpass RC network.
3. The data slicer of claim 1 or 2, in which the signal level measurement circuit includes
an analog-to-digital converter, and the signal generator includes a digital-to-analog
converter.
4. The data slicer of claim 1, 2 or 3, in which the controller stores one or more reference
values to which it can set the signal generator.
5. The data slicer of claim 1, 2, 3 or 4, in which the controller receives an indication
as to whether or not each frame of received data contained errors, and which stores
a reference value only when its corresponding frame contained no errors.
6. A method for squaring up a digital data signal, which method comprises the following
steps:
• receiving an input data signal;
• determining a reference level;
• applying the input signal and the reference level to the inputs of a comparator,
which comparator's output comprises the squared-up output data signal;
• measuring the reference level after a first predetermined time period;
• maintaining the reference level at a desired level throughout a second predetermined
time period;
• storing the measured reference level.
7. The method of claim 6, in which the input signal is DC-coupled to the first input
of the comparator.
8. The method of claim 6 or 7, in which the step of determining a reference level is
accomplished by applying the input signal to a lowpass filter.
9. The method of claim 7, in which the step of determining the reference level includes
the following substeps:
• setting a lowpass filter to an initial condition prior to receiving desired input
data;
• applying the desired DC-coupled input signal to the lowpass filter, which filter's
output comprises the reference level.
10. The method of claim 9, in which the lowpass filter is set to an initial condition
by applying a previously-stored voltage level to the filter.
11. The method of claim 10, in which a separate reference level is stored for each of
a plurality of communications channels, and the previously-stored voltage level which
is applied to the lowpass filter is the reference level stored during a prior communication
on the channel over which the desired input data is currently being received.
12. The method of any of claim 6 to 11, in which the step of storing the measured reference
level is comprised of the following substeps:
• determining whether any errors were present in the received squared-up digital data
signal;
• storing the measured reference level only if no errors were present in the squared-up
digital data signal received.
13. The method of any of claim 6 to 12, in which the desired level is equal to the measured
level.
14. The method of any of claim 6 to 12, in which the desired level is equal to the measured
level, unless the measured level is greater than a predetermined upper limit in which
case the desired level is equal to the upper limit, or if the measured level is below
a predetermined lower limit in which case the desired level is equal to the lower
limit.