SEMICONDUCTOR STRUCTURES HAVING A STRAIN COMPENSATED LAYER AND METHOD OF FABRICATION - Patent 1183761

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EP 1 183 761 A2

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(88)	Date of publication A3:
	04.01.2001

(43)	Date of publication:
	06.03.2002 Bulletin 2002/10

(21)	Application number: 00940681.0

(22)	Date of filing: 01.03.2000

(51)	International Patent Classification (IPC)⁷: H01S 5/34, H01L 29/15, H01L 31/0352, H01L 33/00

(86)	International application number:
	PCT/IB0000/892

(87)	International publication number:
	WO 0058/999 (05.10.2000 Gazette 2000/40)

(84)	Designated Contracting States:
	AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

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Priority:

26.03.1999 US 277319

(71)	Applicant: Matsushita Electronics Corporation
	Kadoma-shi, Osaka 571-8501 (JP)

(72)	Inventors:
	TAKAYAMA, Toru Menlo Park, CA 94015 (US) BABA, Takaaki Los Altos, CA 94024 (US) HARRIS, James, S., Jr. Stanford, CA 94305 (US)

(74)	Representative: Senior, Alan Murray et al
	J.A. KEMP & CO., 14 South Square, Gray's Inn London WC1R 5LX London WC1R 5LX (GB)

(54)	SEMICONDUCTOR STRUCTURES HAVING A STRAIN COMPENSATED LAYER AND METHOD OF FABRICATION