(19)
(11) EP 1 187 027 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
07.08.2002 Bulletin 2002/32

(43) Date of publication A2:
13.03.2002 Bulletin 2002/11

(21) Application number: 01000432.3

(22) Date of filing: 07.09.2001
(51) International Patent Classification (IPC)7: G06F 13/28, G06F 13/40
(84) Designated Contracting States:
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
Designated Extension States:
AL LT LV MK RO SI

(30) Priority: 08.09.2000 US 231383 P

(71) Applicant: Texas Instruments Inc.
Dallas, Texas 75251 (US)

(72) Inventors:
  • Jahnke, Steven R.
    Tokyo, 150-0012 (JP)
  • Hamakawa, Hiromichi
    Ibaraki, 300-0521 (JP)

(74) Representative: Holt, Michael 
Texas Instruments Ltd., EPD MS/13, 800 Pavilion Drive
Northampton Business Park, Northampton NN4 7YL
Northampton Business Park, Northampton NN4 7YL (GB)

   


(54) Micro-controller DMA operation with adjustable word size transfers and address alignment/incrementing


(57) A micro-controller direct memory access (DMA) unit includes hardware support for single read of the source address at a source word size but writes to the target address at an independent target word size. This permits, for example, a single read of the source address at a larger word size and multiple sub-word sized writes to the target address. This is enabled by independent control register storage of a source word size (321), a source increment size (323), a target word size (322) and a target increment size (324). A byte shifter/register (305) that will shift a full byte at a time to the next lower byte position allowing transfer of a large word to a destination having a small word size.






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