(19)
(11) EP 1 198 004 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
01.10.2003 Bulletin 2003/40

(43) Date of publication A2:
17.04.2002 Bulletin 2002/16

(21) Application number: 01000533.8

(22) Date of filing: 12.10.2001
(51) International Patent Classification (IPC)7: H01L 23/522, H01L 23/485
(84) Designated Contracting States:
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
Designated Extension States:
AL LT LV MK RO SI

(30) Priority: 13.10.2000 US 240452 P

(71) Applicant: Texas Instruments Inc.
Dallas, Texas 75251 (US)

(72) Inventor:
  • Efland, Taylor R.
    Richardson, TX 75082 (US)

(74) Representative: Holt, Michael 
Texas Instruments Ltd., EPD MS/13, 800 Pavilion Drive
Northampton Business Park, Northampton NN4 7YL
Northampton Business Park, Northampton NN4 7YL (GB)

   


(54) Semiconductor device having power distribution lines thereon


(57) An integrated circuit (IC) chip (200), mounted on a leadframe, has a network of power distribution lines (251,252) deposited on the surface of the chip so that these lines are located over active components (202,203) of the IC, connected vertically by metal-filled vias (260) to selected active components below the lines, and also by conductors (240,241) to segments of the leadframe. The network relocates most of the conventional power distribution interconnections from the circuit level to the surface network. The network is electrically connected to selected active components by metal-filled vias. The network relocates most of the bond pads dedicated to power supply from the conventional alignment along the chip periphery onto the newly created bondable lines. The network is deposited and patterned in wafer processing as a sequence of metal layers specifically suited for providing power current and electrical ground potential. The network has attachable outermost metal surface and is laid out so that network portions form pads convenient for attaching balls of bonding wires or solder.







Search report