The present invention relates in general to the field of voltage regulators, in particular switching voltage regulators operating according to the buck converter principle.
Electronic devices like computer processors or other loads driven by DC power require very often one or more stable DC supply voltages for operation. In the past these DC supply voltages have been conventionally obtained with the aid of AC-DC converters which employ typical transformers and rectifiers as well as suitable capacitors and filters to convert an AC supply voltage to a determined DC voltage. However, the voltage requirements of electronic loads such as computer processors and logic ICs are relatively high with respect to the DC voltage stability. One reason is that processing circuits may process different amounts of data at various points in time which means that their workloads and hence energy requirements vary significantly. Such loads would benefit greatly from an adjustable and well-defined DC supply voltage.
There exist conventional voltage regulator circuits that provide a constant output voltage of a predetermined value by monitoring the output and using feedback to keep the output constant. In a typical pulse width modulation (PWM) regulator circuit, a square wave is provided to the control terminal of the switching device to control its ON and OFF states. Since increasing the ON time of the switching device increases the output voltage and vice versa, the output voltage may be controlled by manipulating the duty cycle of the square wave. This manipulation is accomplished by a control circuit which continually compares the output voltage to a reference voltage and adjusts the duty cycle of the square wave to maintain a constant output voltage.
The US-PS 5,945,820 discloses a DC-DC switching regulator which converts a supplied DC voltage to a DC output voltage for driving a load using a DC-DC buck converter operated with fixed-width pulses at an instantaneous switching rate. The regulator has a feedback for computing a subsequent switching rate based on the instantaneous switching rate, an output frequency derived from output voltage by a ring oscillator and a desired frequency provided by a frequency signaling device or a frequency signaling port of the load. By altering the desired frequency the load communicates its power needs. The regulator can be used in the low-power regime and at high-power levels.
Another type of voltage regulator is described in the WO 96/10287. This type of voltage regulator is also called a buck converter and it achieves high efficiency by automatically switching between a pulse frequency modulation (PFM) mode and a pulse-width modulation (PWM) mode. Switching between the modes of voltage regulation is accomplished by monitoring the output voltage and the output current, wherein the regulator operates in PFM mode at small output currents and in PWM mode at moderate to large output currents. PFM mode maintains a constant output voltage by forcing the switching device to skip cycles when the output voltage exceeds its nominal value. In PWM mode, a PWM signal having a variable duty cycle controls the switching device. A constant output voltage is maintained by feedback circuitry which alters the duty cycle of the PWM signal according to fluctuations in the output voltage. In a PFM mode of voltage regulation the system provides better efficiency at small output current levels than does a PWM mode.
As mentioned the PFM is a mode of the buck derived converter, which is used for very low load currents. In this mode the converter senses the output voltage with a comparator, which triggers when the output voltage is too low. It effects the turning on of the switching element, i.e. the power transistor, until the current through the inductor reaches a determined value, at which the output transistor is turned off. Therefore the frequency of the converter varies depending on the load. One of the problems that occurs in the PFM mode is when the DC/DC converter is overloaded. A further problem which is not yet solved is the switch back from the PFM mode to the PWM mode, in particular the finding of a digital signal which can switch the converter from PFM to PWM.
In most commercial products like e.g. from Linear Technologies and Maxim a load current sensing scheme is used to determine when to change to the PWM mode in case of an overload condition in the PFM mode.
It is therefore one object of the present invention to provide a method performed by a voltage regulator which addresses the above mentioned problems. In particular it is an object of the present invention to provide a solution of an overload condition occurring during the performance of the PFM mode. It is a further object of the present invention to provide for a switch from the PFM mode to the PWM mode.
These objects are solved by the features of the appended claim 1. Exemplary and adventageous embodiments are given in the subclaims.
It is one essential aspect of the present invention that in a method performed by a voltage regulator a limitation of the pulse frequency is introduced in the PFM mode. The pulse frequency is effectively limited by introducing a time delay in the second feedback circuit of the voltage regulator, i.e. the feedback circuit of the PFM mode. Due to the time delay the pulses generated and output to the LC-filter are spread in time so that the pulse frequency is effectively limited.
The invention particularly relates to a method performed by voltage regulator comprising the steps of generating a regulated output voltage and an output current at an output terminal of the regulator using a switching device for providing the output current, said switching device having an ON state and an OFF state, controlling the switching device with a first control circuit functioning in a pulse width modulation (PWM) mode, said first control circuit comprising a square wave generator outputting a square wave having a duty cycle corresponding to said regulated output voltage at the output terminal, wherein the square wave generator controls the ON and OFF states of the switching device, and a first feedback circuit for generating an error signal based on a difference between a voltage corresponding to the output voltage and a first reference voltage and varying a duty cycle of the square wave generator in response to the error signal to cause the output voltage to be of a predetermined voltage level, and controlling the switching device with a second control circuit, wherein the second control circuit comprises a signal generator outputting a switching signal having a fixed duty cycle, said signal generator controlling the ON and OFF states of said switching device, and a second feedback circuit functioning in a pulse frequency modulation (PFM) mode, wherein a time delay is introduced in the second feedback circuit in order to introduce a limitation of the pulse frequency.
The second feedback circuit may comprise a current comparator sensing the current flowing through the switching device and a first voltage comparator sensing the output voltage of the voltage regulator. The current comparator may be set such that it detects a situation in which the current exceeds a predetermined level at the rising edge of a pulse thereby effecting turn off of the switching device and turn on of the time delay, and the voltage comparator may be set such that it detects a situation in which the output voltage falls below a desired output voltage, thereby effecting turn on of the switching device.
The time delay may be introduced in such a way in the second feedback circuit that the switching device is not allowed to turn ON until the time delay is OFF.
The voltage regulator may also comprise a second voltage comparator which effects a switchback from the PFM mode to the PWM mode, if the output voltage falls below a desired output voltage for a predetermined amount, e.g. 60mV. The output voltage of the regulator is sensed by the second voltage comparator and the second voltage comparator outputs a digital signal if the output voltage falls below the desired output voltage for more than the predetermined amount. This digital signal then effects the switchback from the PFM mode to the PWM mode.
In an embodiment of the voltage regulator as used in the inventive method a driver circuit may be used as the square wave generator in the PWM mode as well as the signal generator in the PFM mode.
The switching device may be comprised of a transistor, in particular of a power transistor.
In the following details of an embodiment and of a possible switching scheme showing output voltage and inductor current are described with respect to the accompanying drawings, in which
The time variation of the inductor current (a) and the output voltage (b) as depicted in Fig. 1 shows an embodiment in which the time delay is triggered when the current comparator detects a so called peak current, i.e. a predetermined current level and turns off the switching device upon detection of the peak current. On the other hand the first voltage comparator detects a situation in which the output voltage becomes comparable to the desired output voltage and turns on the output transistor upon detection.
The circuit scheme as depicted in Fig. 2 is only the part of the voltage regulator circuit which performs the PFM mode. It does not include the control for the PWM mode nor the digital control which decides when it has to be in the PFM mode or the PWM mode. For details of the buck converter switching mechanism reference is again made to the WO 96/10287.Several parts and devices of the depicted switching circuit are numbered and listed in the accompanying list of reference signs.
The switching device 1 is a power transistor which has an ON state and an OFF state and which is controlled by a driver 2 which functions as a signal generator in the PFM mode. The driver 2 can be shared between the PWM mode and the PFM mode and in the PWM mode it can be used as a square wave generator.
The difference with respect to the state of the art lies in the introduction of a frequency limitation by introducing a time delay in the feedback circuit of the PFM mode. When the power transistor 1 is turned ON , or even better if it is turned OFF (as in Fig. 1 ), a time delay is triggered. If the voltage comparator triggers before the time delay turns OFF, then an overload condition occurs. It is possible to use this signal to generate the switchback to PWM. A frequency limitation may also be effected by not allowing the power transistor to turn ON until the time delay is OFF. Since the frequency is proportional to the load current, this is also a current limitation, therefore the output voltage will decrease, and another voltage comparator like the second voltage comparator 4 can sense this condition. The lower voltage to be sensed by the second voltage comparator 4 must of course lay in the voltage range of the specifications. This allows also possible temporary conditions where the converter in PFM mode may be overloaded for brief period of time.