Method for reducing power consumption of CPU, electronic apparatus, and recording medium having power consumption reduction program recorded thereon

(19)

(11)

EP 1 215 561 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	31.12.2008 Bulletin 2009/01

(43)	Date of publication A2:
	19.06.2002 Bulletin 2002/25

(21)	Application number: 01129000.4

(22)	Date of filing: 06.12.2001

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International Patent Classification (IPC):

G06F 1/32^(2006.01)

(84)	Designated Contracting States:
	AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
	Designated Extension States:
	AL LT LV MK RO SI

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Priority:

14.12.2000 JP 2000379565

(71)	Applicant: Sumitomo Wiring Systems, Ltd.
	Yokkaichi-city, Mie Aichi 510-8503 (JP)

(72)	Inventor:
	Sumida, Yoshitaka Yokkaichi-city, Mie, 510-8503 (JP)

(74)	Representative: Herzog, Markus et al
	Weickmann & Weickmann Patentanwälte Postfach 86 08 20 81635 München 81635 München (DE)

(54)	Method for reducing power consumption of CPU, electronic apparatus, and recording medium having power consumption reduction program recorded thereon

(57) Method and apparatus for reducing electrical power consumption of an electronic unit provided with a central processing unit (CPU). The CPU is returned to a normal operation state at regular intervals when the CPU has been placed in a sleep state. The CPU outputs a clear signal to a monitoring circuit, and makes reference to an actuation signal for an external device, such as, for example, a motor from a control switch to place the CPU in the sleep state at a time other than a time when reference is made to the clear signal and the input signal. When the CPU has been released from the sleep state, reference to an output of the clear signal and the input signal and an output of only the clear signal are repeated at regular intervals and at a predetermined frequency.

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