(19)
(11) EP 1 223 678 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
22.10.2003 Bulletin 2003/43

(43) Date of publication A2:
17.07.2002 Bulletin 2002/29

(21) Application number: 01130717.0

(22) Date of filing: 21.12.2001
(51) International Patent Classification (IPC)7: H03M 13/27
(84) Designated Contracting States:
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
Designated Extension States:
AL LT LV MK RO SI

(30) Priority: 27.12.2000 JP 2000397073

(71) Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Kadoma-shi, Osaka 571-8501 (JP)

(72) Inventor:
  • Uto, Hiroshi
    Ibaraki-shi, Osaka 567-0861 (JP)

(74) Representative: Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät 
Maximilianstrasse 58
80538 München
80538 München (DE)

   


(54) Interleave circuit, de-interleave circuit and xDSL modem


(57) When a frame length N of input data is an even number, a read address generator generates twice in succession an address at which head byte data of each frame of the input data is stored. The head byte data of each frame of the input data is thus read from a memory twice in succession. The data of the frame length (N + 1) having the head byte data of each frame inserted as a dummy byte is then written to another memory according to a write address from a write address generator.






Search report