WAFER BONDING TECHNIQUES TO MINIMIZE BUILT-IN STRESS OF SILICON MICROSTRUCTURES AND MICRO-MIRRORS - Patent 1254479

(19)

(11)

EP 1 254 479 A1

(12)

(43)	Date of publication:
	06.11.2002 Bulletin 2002/45

(21)	Application number: 01903124.4

(22)	Date of filing: 18.01.2001

(51)	International Patent Classification (IPC)⁷: H01L 21/20, H01L 21/762

(86)	International application number:
	PCT/US0101/758

(87)	International publication number:
	WO 0105/4176 (26.07.2001 Gazette 2001/30)

(84)	Designated Contracting States:
	AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
	Designated Extension States:
	AL LT LV MK RO SI

(30)

Priority:

18.01.2000 US 176325 P
16.11.2000 US 715916

(71)	Applicant: XROS, Inc., Nortel Networks
	Santa Clara, CA 95054 (US)

(72)	Inventor:
	SLATER, Timothy, G. San Francisco, CA 94110 (US)

(74)	Representative: Charig, Raymond Julian
	Eric Potter Clarkson,Park View House,58 The Ropewalk Nottingham NG1 5DD Nottingham NG1 5DD (GB)

(54)	WAFER BONDING TECHNIQUES TO MINIMIZE BUILT-IN STRESS OF SILICON MICROSTRUCTURES AND MICRO-MIRRORS