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<ep-patent-document id="EP00971869B1" file="EP00971869NWB1.xml" lang="en" country="EP" doc-number="1258024" kind="B1" date-publ="20100721" status="n" dtd-version="ep-patent-document-v1-4">
<SDOBI lang="en"><B000><eptags><B001EP>......DE....FRGB..IT....NL..........................................................................</B001EP><B003EP>*</B003EP><B005EP>J</B005EP><B007EP>DIM360 Ver 2.15 (14 Jul 2008) -  2100000/0</B007EP></eptags></B000><B100><B110>1258024</B110><B120><B121>EUROPEAN PATENT SPECIFICATION</B121></B120><B130>B1</B130><B140><date>20100721</date></B140><B190>EP</B190></B100><B200><B210>00971869.3</B210><B220><date>20001027</date></B220><B240><B241><date>20020525</date></B241><B242><date>20060413</date></B242></B240><B251EP>en</B251EP><B260>en</B260></B200><B300><B310>9947639</B310><B320><date>19991029</date></B320><B330><ctry>KR</ctry></B330></B300><B400><B405><date>20100721</date><bnum>201029</bnum></B405><B430><date>20021120</date><bnum>200247</bnum></B430><B450><date>20100721</date><bnum>201029</bnum></B450><B452EP><date>20100212</date></B452EP></B400><B500><B510EP><classification-ipcr sequence="1"><text>H01J  17/49        20060101AFI20010509BHEP        </text></classification-ipcr><classification-ipcr sequence="2"><text>H01J  11/02        20060101ALI20010509BHEP        </text></classification-ipcr></B510EP><B540><B541>de</B541><B542>PLASMAANZEIGEVORRICHTUNG</B542><B541>en</B541><B542>PLASMA DISPLAY PANEL</B542><B541>fr</B541><B542>ECRAN A PLASMA</B542></B540><B560><B561><text>JP-A- 6 283 108</text></B561><B561><text>JP-A- 11 045 663</text></B561><B561><text>KR-A- 98 048 662</text></B561><B561><text>KR-A- 98 052 817</text></B561><B561><text>KR-A- 99 016 640</text></B561><B561><text>US-A- 5 742 122</text></B561><B562><text>PATENT ABSTRACTS OF JAPAN vol. 1999, no. 13, 30 November 1999 (1999-11-30) &amp; JP 11 213904 A (LG ELECTRONICS INC), 6 August 1999 (1999-08-06) -&amp; US 6 339 292 B1 (HA HONG JU) 15 January 2002 (2002-01-15)</text></B562><B562><text>PATENT ABSTRACTS OF JAPAN vol. 018, no. 116 (E-1515), 24 February 1994 (1994-02-24) &amp; JP 05 314911 A (NEC CORP), 26 November 1993 (1993-11-26)</text></B562><B565EP><date>20050928</date></B565EP></B560></B500><B700><B720><B721><snm>CHO, Guang, Sup</snm><adr><str>106-203 Hanshin 2th Apt.,
Shinbanpo-2-Gigu</str><city>73 Zamwon-dong,
Socho-gu,
Seoul 137-030</city><ctry>KR</ctry></adr></B721><B721><snm>CHOI, Eun, Ha</snm><adr><str>110-502 Life Apt.,
Joongkae-dong,
Nowon-gu</str><city>Seoul 139-220</city><ctry>KR</ctry></adr></B721><B721><snm>KIM, June, Dong</snm><adr><str>331-106 Shinbanpo 19th Apt.,
61 Zamwon-dong</str><city>Socho-gu,
Seoul 137-030</city><ctry>KR</ctry></adr></B721><B721><snm>JU, Young, Dae</snm><adr><str>920-1 Bisan-7-dong,
Suh-gu</str><city>Daegu-shi 703-047</city><ctry>KR</ctry></adr></B721><B721><snm>HAN, Jung, Gwan</snm><adr><str>1-1302 Woosung Apt.,
Songnae-dong,
Sosa-gu</str><city>Bucheon-shi,
Kyoungki-do 422-040</city><ctry>KR</ctry></adr></B721></B720><B730><B731><snm>Orion PDP Co., Ltd.</snm><iid>07751490</iid><irf>P.6908 EPP</irf><adr><str>257 Gongdan-dong, 
Gumi-si</str><city>Kyoungsangbuk-do 730--904</city><ctry>KR</ctry></adr></B731></B730><B740><B741><snm>Evens, Paul Jonathan</snm><sfx>et al</sfx><iid>00083931</iid><adr><str>Maguire Boss 
24 East Street</str><city>St. Ives
Cambridgeshire PE27 5PD</city><ctry>GB</ctry></adr></B741></B740></B700><B800><B840><ctry>DE</ctry><ctry>FR</ctry><ctry>GB</ctry><ctry>IT</ctry><ctry>NL</ctry></B840><B860><B861><dnum><anum>KR2000001225</anum></dnum><date>20001027</date></B861></B860><B870><B871><dnum><pnum>WO2001031675</pnum></dnum><date>20010503</date><bnum>200118</bnum></B871></B870><B880><date>20021120</date><bnum>200247</bnum></B880></B800></SDOBI><!-- EPO <DP n="1"> -->
<description id="desc" lang="en">
<heading id="h0001"><b>BACKGROUND OF THE INVENTION</b></heading>
<heading id="h0002"><u>Field of the Invention</u></heading>
<p id="p0001" num="0001">The present invention relates to a plasma display panel (PDP), and more particularly, to a PDP having an improved structure of a sustain electrode which is formed on an upper substrate of the PDP used in various flat panel display devices such as TV or monitors.</p>
<heading id="h0003"><u>Discussion of the Related Art</u></heading>
<p id="p0002" num="0002"><figref idref="f0001">Fig. 1</figref> is a schematic view of a unit pixel formed on an upper substrate of a related art PDP.</p>
<p id="p0003" num="0003">Referring to <figref idref="f0001">Fig. 1</figref>, two transparent electrodes 1 are deposited on the upper substrate at regular intervals, and bus electrodes 2 for connection to a power source are deposited on both ends of the transparent electrode 1. A plasma is formed in a unit pixel in such a manner that a power source is supplied through the bus electrodes 2 to maintain discharge between the transparent electrodes 1 having regular intervals.</p>
<p id="p0004" num="0004"><figref idref="f0002">Figs. 2a and 2b</figref> illustrate a related art PDP.</p>
<p id="p0005" num="0005">As shown in <figref idref="f0002">Fig. 2a</figref>, horizontal transparent and bus electrodes 1 and 2 are formed on a transparent upper substrate 7. As shown in <figref idref="f0002">Fig. 2b</figref>, vertical signal electrodes 5 are formed on a lower substrate 6 at regular intervals, vertical sidewalls 4 are formed on the signal electrodes 5, and phosphors of R, G, and B are deposited between the sidewalls 4. Then, the upper substrate 7 is attached to the lower substrate 6.<!-- EPO <DP n="2"> --></p>
<p id="p0006" num="0006">In the related art PDP having the above electrode structure, the discharge and sustain electrodes are flush with each other and the quantity of the plasma is proportional to an electrode area.</p>
<p id="p0007" num="0007">Since an area of the electrode is limited due to a limited size of the unit pixel, the plasma generating quantity is also limited. The energy of the plasma is continuously lost through an outer wall and the like. The energy of the plasma is much required to maintain discharge.</p>
<p id="p0008" num="0008">If the plasma generating quantity is small, much more energy is required to maintain discharge. For this reason, energy efficiency of the PDP is reduced. Also, in the related art PDP having the above electrode structure, efficiency is reduced if the size of the unit pixel is small. In this case, it is difficult to obtain high picture quality.</p>
<heading id="h0004"><b>SUMMARY OF THE INVENTION</b></heading>
<p id="p0009" num="0009">Accordingly, the present invention is directed to a PDP that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.</p>
<p id="p0010" num="0010">An object of the present invention is to provide a PDP which improves discharge efficiency by reducing a discharge voltage and increasing a volume of a plasma.</p>
<p id="p0011" num="0011">Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the scheme particularly pointed out in the written description and claims hereof as well as the<!-- EPO <DP n="3"> --> appended drawings.</p>
<p id="p0012" num="0012">To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided in accordance with the present invention a plasma display panel (PDP) provided with upper and lower substrates aligned in parallel at regular intervals, first and second electrodes formed on the upper substrate in one unit pixel, third electrodes formed on the lower substrate to correspond to the first and second electrodes, and bus lines which connect the first and second electrodes with adjacent first and second electrodes, the PDP comprises fence-type electrodes extended toward the lower substrate; characterised in that a sidewall is formed in a rectangular frame to divide the pixels on the upper substrate, and the fence-type electrodes are formed on the sidewall.</p>
<p id="p0013" num="0013">The invention is defined by the claims.</p>
<p id="p0014" num="0014">The prior art document <patcit id="pcit0001" dnum="JP11213904A"><text>JP 11 213904 A</text></patcit> (LG ELECTRONICS INC) discloses a plasma display panel with fence-type electrodes formed on the sidewalls of channels. This geometry however suffers from a reduced efficiency.</p>
<p id="p0015" num="0015">The following does not form part of the invention but is added as additional information only: the PDP may comprise fence-type electrodes extended toward the lower substrate in a corner of an adjacent pixel of the first and second electrodes.</p>
<p id="p0016" num="0016">In one embodiment of the PDP according to the present invention, the fence-type electrodes are made of an opaque metal material. In another embodiment, the fence-type electrodes connected with the first and second electrodes are connected with the fence-type electrodes connected with the first and second electrodes of an adjacent pixel by a bus electrode formed on the sidewall. In another embodiment, the first and second electrodes and the fence-type electrodes are formed symmetrically in a diagonal direction within each unit pixel.</p>
<p id="p0017" num="0017">It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.</p>
<heading id="h0005"><b>BRIEF DESCRIPTION OF THE DRAWINGS</b></heading>
<p id="p0018" num="0018">The invention will be described in detail with reference to the following drawings in which like reference<!-- EPO <DP n="4"> --><!-- EPO <DP n="5"> --> numerals refer to like elements wherein:
<ul id="ul0001" list-style="none" compact="compact">
<li><figref idref="f0001">Fig. 1</figref> is a schematic view showing a unit pixel formed on an upper substrate of a related art PDP;</li>
<li><figref idref="f0002">Fig. 2a</figref> is a schematic view showing an upper substrate of a related art PDP provided with an electrode of <figref idref="f0001">Fig. 1</figref>;</li>
<li><figref idref="f0002">Fig. 2b</figref> is a schematic view of a lower substrate of a PDP corresponding to <figref idref="f0002">Fig. 2a</figref>;</li>
<li><figref idref="f0003">Fig. 3</figref> is a schematic view of an electrode of a unit pixel formed on an upper substrate of a PDP according to the first embodiment of the present invention;</li>
<li><figref idref="f0003">Fig. 4</figref> is a schematic view of an upper substrate of a PDP provided with an electrode of <figref idref="f0003">Fig. 3</figref>;</li>
<li><figref idref="f0004">Fig. 5</figref> is a schematic view of an upper substrate of a PDP according to the second embodiment of the present invention; and</li>
<li><figref idref="f0004">Fig. 6</figref> is a schematic view of an upper substrate of a PDP according to the third embodiment of the present invention.</li>
</ul></p>
<heading id="h0006"><b>DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS</b></heading>
<p id="p0019" num="0019">Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.</p>
<p id="p0020" num="0020"><figref idref="f0003">Fig. 3</figref> is a schematic view of an electrode of a unit pixel formed on an upper substrate of a PDP according to the first embodiment of the present invention.</p>
<p id="p0021" num="0021">A lower substrate of a PDP according to the present invention has the same structure as that of the related art PDP. Accordingly, the upper substrate of a PDP according to the present invention will be described below.<!-- EPO <DP n="6"> --></p>
<p id="p0022" num="0022">An electrode structure of one unit pixel is shown in <figref idref="f0003">Fig. 3</figref>. Referring to <figref idref="f0003">Fig. 3</figref>, the unit pixel includes two portions, wherein a left side portion is defined as a first electrode and a right side portion is defined as a second electrode.</p>
<p id="p0023" num="0023">A pair of transparent electrodes 1 are deposited on the bottom surface of the unit pixel at regular intervals. An opaque metal fence-type electrode 3 is partially formed in a corner portion of the unit pixel to be partially projected from a corner portion of an adjacent pixel to the lower substrate. A bus electrode 2 is connected to the fence-type electrode 3.</p>
<p id="p0024" num="0024">In other words, a discharge sustain electrode structure of a fence type having two portions is formed. In the present invention, a pair of the transparent electrodes 1 are referred to as a discharge sustain electrode.</p>
<p id="p0025" num="0025"><figref idref="f0003">Fig. 4</figref> is a schematic view of the upper substrate of a PDP provided with the electrode of <figref idref="f0003">Fig. 3</figref>. The electrode of the upper substrate of <figref idref="f0003">Fig. 4</figref> is orthogonal to the electrode(ex, signal electrode) of the lower substrate(not shown). In <figref idref="f0003">Fig. 4</figref>, an electrode structure of 6 unit pixels is exemplified.</p>
<p id="p0026" num="0026">A reference numeral 1 denotes a transparent electrode, a reference numeral 2 denotes a bus electrode, a reference numeral 3 denotes a fence-type electrode, a reference numeral 7 denotes an upper substrate, a reference numeral 8 denotes a horizontal sidewall, and a reference numeral 9 denotes a vertical sidewall.</p>
<p id="p0027" num="0027">Lattice shaped (matrix shaped) sidewalls 8 and 9 are formed in a rectangular frame on the upper substrate 7 in horizontal and vertical directions. Thus, an individual<!-- EPO <DP n="7"> --> discharge space is formed for a unit pixel.</p>
<p id="p0028" num="0028">The lattice shaped sidewalls 8 and 9 improve contrast. A pair of the transparent electrodes 1 are deposited on a bottom surface of the upper substrate 7 at regular intervals for a unit pixel in a horizontal direction. An opaque metal fence-type electrode 3 is deposited inside the sidewalls 8 and 9, so as to increase the plasma generating quantity of a corresponding pixel during individual discharge.</p>
<p id="p0029" num="0029">In <figref idref="f0003">Fig. 4</figref>, the bus electrode 2 is deposited on the horizontal sidewall 8 so that it is to be connected with the transparent electrodes 1 using the fence-type electrode 3 as a medium. The heights of the sidewalls 8 and 9 are lower than the height of a sidewall of the lower substrate.</p>
<p id="p0030" num="0030"><figref idref="f0004">Fig. 5</figref> is a schematic view of an upper substrate of a PDP according to the second embodiment of the present invention. Referring to <figref idref="f0004">Fig. 5</figref>, transparent electrodes are aligned along a fence-type electrode to extend a discharge path of a sustain electrode, thereby improving discharge density.</p>
<p id="p0031" num="0031">In <figref idref="f0004">Fig. 5</figref>, an electrode structure of 6 unit pixels is exemplified. A reference numeral 1 denotes a transparent electrode, a reference numeral 2 denotes a bus electrode, a reference numeral 3 denotes a fence-type electrode, a reference numeral 7 denotes an upper glass substrate, a reference numeral 8 denotes a horizontal sidewall, and a reference numeral 9 denotes a vertical sidewall.</p>
<p id="p0032" num="0032">A pair of the transparent electrodes 1 are longitudinally formed in a vertical direction at regular intervals in one unit pixel. Each of the transparent electrodes 1 is slanted toward either upper or lower directions. An opaque metal fence-type electrode 3 is<!-- EPO <DP n="8"> --> deposited inside the sidewalls 8 and 9 surrounding the outer wall of the transparent electrodes 1 so as to increase the plasma generating quantity of a corresponding pixel during discharge of an individual pixel.</p>
<p id="p0033" num="0033">The fence-type electrodes 3 and the transparent electrodes 1 per unit pixel are symmetrically formed in a diagonal direction.</p>
<p id="p0034" num="0034">The bus electrode 2 is deposited on the horizontal sidewall 8 to be connected with the transparent electrode 1 using the fence-type electrode 3 as a medium. The heights of the sidewalls 8 and 9 are lower than that of a sidewall of the lower substrate.</p>
<p id="p0035" num="0035"><figref idref="f0004">Fig. 6</figref> is a schematic view of an upper substrate of a PDP according to the third embodiment of the present invention. Referring to <figref idref="f0004">Fig. 6</figref>, a fence-type electrode type upper substrate having a long corner electrode structure is formed orthogonally to the electrodes of <figref idref="f0003">Fig. 3</figref>. In <figref idref="f0004">Fig. 6</figref>, an electrode structure of 6 unit pixels is exemplified. A reference numeral 1 denotes a transparent electrode, a reference numeral 2 denotes a bus electrode, a reference numeral 3 denotes a fence-type electrode, a reference numeral 7 denotes an upper glass substrate, a reference numeral 8 denotes a horizontal sidewall, and a reference numeral 9 denotes a vertical sidewall.</p>
<p id="p0036" num="0036">In <figref idref="f0004">Fig. 6</figref>, the bus electrode 2 is formed in the same direction (vertical direction) as that of a sidewall of a lower substrate (not shown), so that a pair of discharge sustain electrodes respectively correspond to respective phosphors. A signal electrode of the lower electrode is formed in a horizontal direction perpendicular to the sidewall of the lower substrate.<!-- EPO <DP n="9"> --></p>
<p id="p0037" num="0037">A pair of the transparent electrodes 1 are deposited on the upper glass substrate 7 in a vertical direction at regular intervals in a unit pixel. The vertical sidewall 9 of the upper substrate is formed in the same direction as a vertical sidewall 4 (see <figref idref="f0002">Fig. 2</figref>) of the lower substrate. The horizontal sidewall 8 is additionally formed.</p>
<p id="p0038" num="0038">An opaque metal fence-type electrode 3 is deposited inside the sidewalls 8 and 9 of a rectangular frame so as to increase the plasma generating quantity of a corresponding pixel during discharge of an individual pixel.</p>
<p id="p0039" num="0039">The bus electrode 2 is deposited on the horizontal sidewall 8 to be connected with a power source in the vertical direction. The heights of the sidewalls 8 and 9 are lower than the height of a sidewall of the lower substrate.</p>
<p id="p0040" num="0040">Consequently, in <figref idref="f0004">Figs. 5 and 6</figref>, the length of a corner portion of the transparent electrode 1 is longer than that of a corner portion of the transparent electrode in the related art PDP.</p>
<p id="p0041" num="0041">In the aforementioned electrode structure of <figref idref="f0004">Fig. 6</figref>, a plasma is generated by discharge between two transparent electrodes 1 having a long corner portion between the sidewalls. Also, an electrode structure with high efficiency is provided, in which an area of the electrode is maximized and the plasma generating quantity is increased between the transparent electrodes having a long corner portion.</p>
<p id="p0042" num="0042">In the aforementioned PDP according to the first to third embodiments of the present invention, the opaque metal fence-type electrode 3 is deposited on the sidewalls 8 and 9 of the upper substrate to utilize the area of the electrode 8<!-- EPO <DP n="10"> --> to the utmost and thus reduce the discharge voltage. The fence-type electrode 3 minimizes loss of the plasma generated during discharge in an individual unit pixel to increase the plasma generating quantity.</p>
<p id="p0043" num="0043">As the electrode area is widened, a plasma formation space is increased and plasma energy loss is decreased, thereby performing stabilized space discharge. Moreover, interaction between adjacent pixels is prevented by individualizing the unit pixels by the side wall. The size of the pixels is decreased to obtain a high quality screen.</p>
<p id="p0044" num="0044">As aforementioned, the PDP according to the present invention has the following advantages.</p>
<p id="p0045" num="0045">Since the electrode of the upper substrate has a fence-type electrode structure, the discharge voltage is reduced and the volume of the plasma is increased, thereby improving discharge efficiency.</p>
<p id="p0046" num="0046">The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teachings can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art.</p>
</description><!-- EPO <DP n="11"> -->
<claims id="claims01" lang="en">
<claim id="c-en-01-0001" num="0001">
<claim-text>A plasma display panel (PDP) provided with upper and lower substrates aligned in parallel at regular intervals, first and second electrodes (1) formed on the upper substrate (7) on one unit pixel, third electrodes (5) formed on the lower substrate to correspond to the first and second electrodes (1), and bus lines (2) which connect the first and second electrodes (1) with adjacent first and second electrodes, the PDP comprises fence-type electrodes (3)extended toward the lower substrate;<br/>
<b>characterised in that</b> a sidewall (8)(9) is formed in a rectangular frame to divide the pixels on the upper substrate (7), and the fence-type electrodes (3) are formed on the sidewall (8)(9).</claim-text></claim>
<claim id="c-en-01-0002" num="0002">
<claim-text>The PDP of claim 1, wherein the fence-type electrodes (3) are made of an opaque metal material.</claim-text></claim>
<claim id="c-en-01-0003" num="0003">
<claim-text>The PDP of claim 1, wherein the fence-type electrodes (3) connected with the first and second electrodes (1) are connected with the fence-type electrodes connected with the first and second electrodes of an adjacent pixel by a bus electrode (2) formed on the sidewall (8)(9).</claim-text></claim>
<claim id="c-en-01-0004" num="0004">
<claim-text>The PDP of claim 1, wherein the first and second electrodes (1) and the fence-type electrodes (3) are formed symmetrically in a diagonal direction within each unit pixel.</claim-text></claim>
</claims><!-- EPO <DP n="12"> -->
<claims id="claims02" lang="de">
<claim id="c-de-01-0001" num="0001">
<claim-text>Plasma-Anzeigetafel (PDP) mit oberen und unteren Substraten, die in regelmäßigen Abständen parallel ausgerichtet sind, wobei erste und zweite Elektroden (1) auf dem oberen Substrat (7) auf einem Einheitspixel ausgebildet sind, wobei dritte Elektroden (5) so auf dem unteren Substrat ausgebildet sind, dass sie den ersten und zweiten Elektroden (1) entsprechen, und mit Busleitungen (2), die die ersten und zweiten Elektroden (1) mit benachbarten ersten und zweiten Elektroden verbinden, wobei die PDP zaunähnliche Elektroden (3) umfasst, die in Richtung auf das untere Substrat verlängert sind;<br/>
<b>dadurch gekennzeichnet, dass</b> eine Seitenwand (8)(9) in einem rechteckigen Rahmen ausgebildet ist, um die Pixel auf dem oberen Substrat (7) zu unterteilen, und die zaunähnlichen Elektroden (3) auf der Seitenwand (8)(9) ausgebildet sind.</claim-text></claim>
<claim id="c-de-01-0002" num="0002">
<claim-text>PDP nach Anspruch 1, wobei die zaunähnlichen Elektroden (3) aus einem opaken Metallmaterial gefertigt sind.</claim-text></claim>
<claim id="c-de-01-0003" num="0003">
<claim-text>PDP nach Anspruch 1, wobei die mit den ersten und zweiten Elektroden (1) verbundenen zaunähnlichen Elektroden (3) durch eine auf der Seitenwand (8)(9) ausgebildete Buselektrode (2) mit den zaunähnlichen Elektroden verbunden sind, die mit den ersten und zweiten Elektroden eines Nachbarpixels verbunden sind.</claim-text></claim>
<claim id="c-de-01-0004" num="0004">
<claim-text>PDP nach Anspruch 1, wobei die ersten und zweiten Elektroden (1) und die zaunähnlichen Elektroden (3) symmetrisch in einer diagonalen Richtung innerhalb jedes Einheitspixels ausgebildet sind.</claim-text></claim>
</claims><!-- EPO <DP n="13"> -->
<claims id="claims03" lang="fr">
<claim id="c-fr-01-0001" num="0001">
<claim-text>Écran à plasma (PDP) doté de substrats supérieurs et inférieurs alignés en parallèle à des intervalles réguliers, de premières et deuxièmes électrodes (1) formées sur le substrat supérieur (7) sur une unité pixel, de troisièmes électrodes (5) formées sur le substrat inférieur afin de correspondre aux premières et deuxièmes électrodes (1), et de lignes de bus (2) lesquelles connectent les premières et deuxièmes électrodes (1) à de premières et deuxièmes électrodes adjacentes, l'écran à plasma PDP comportant des électrodes de type délimitation (3) lesquelles s'étendent vers le substrat inférieur ;<br/>
<b>caractérisé en ce qu'</b>une paroi latérale (8) (9) est formée dans un cadre rectangulaire afin de diviser les pixels sur le substrat supérieur (7), et les électrodes de type délimitation (3) sont formées sur la paroi latérale (8) (9).</claim-text></claim>
<claim id="c-fr-01-0002" num="0002">
<claim-text>Écran à plasma (PDP) selon la revendication 1, les électrodes de type délimitation (3) étant fabriquées en une matière métallique opaque.</claim-text></claim>
<claim id="c-fr-01-0003" num="0003">
<claim-text>Écran à plasma (PDP) selon la revendication 1, les électrodes de type délimitation (3) connectées aux premières et deuxièmes électrodes (1) étant connectées aux électrodes de type délimitation connectées aux premières et deuxièmes électrodes d'un pixel adjacent par l'intermédiaire d'une électrode de bus (2) laquelle est formée sur la paroi latérale (8) (9).</claim-text></claim>
<claim id="c-fr-01-0004" num="0004">
<claim-text>Écran à plasma (PDP) selon la revendication 1, les premières et deuxièmes électrodes (1) et les électrodes de type délimitation (3) étant formées symétriquement suivant une direction diagonale au sein de chaque unité pixel.</claim-text></claim>
</claims><!-- EPO <DP n="14"> -->
<drawings id="draw" lang="en">
<figure id="f0001" num="1"><img id="if0001" file="imgf0001.tif" wi="127" he="138" img-content="drawing" img-format="tif"/></figure><!-- EPO <DP n="15"> -->
<figure id="f0002" num="2a,2b"><img id="if0002" file="imgf0002.tif" wi="141" he="233" img-content="drawing" img-format="tif"/></figure><!-- EPO <DP n="16"> -->
<figure id="f0003" num="3,4"><img id="if0003" file="imgf0003.tif" wi="141" he="233" img-content="drawing" img-format="tif"/></figure><!-- EPO <DP n="17"> -->
<figure id="f0004" num="5,6"><img id="if0004" file="imgf0004.tif" wi="141" he="233" img-content="drawing" img-format="tif"/></figure>
</drawings>
<ep-reference-list id="ref-list">
<heading id="ref-h0001"><b>REFERENCES CITED IN THE DESCRIPTION</b></heading>
<p id="ref-p0001" num=""><i>This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.</i></p>
<heading id="ref-h0002"><b>Patent documents cited in the description</b></heading>
<p id="ref-p0002" num="">
<ul id="ref-ul0001" list-style="bullet">
<li><patcit id="ref-pcit0001" dnum="JP11213904A"><document-id><country>JP</country><doc-number>11213904</doc-number><kind>A</kind></document-id></patcit><crossref idref="pcit0001">[0014]</crossref></li>
</ul></p>
</ep-reference-list>
</ep-patent-document>
