(19)
(11) EP 1 269 308 A2

(12)

(88) Date of publication A3:
24.01.2002

(43) Date of publication:
02.01.2003 Bulletin 2003/01

(21) Application number: 01923028.3

(22) Date of filing: 02.04.2001
(51) International Patent Classification (IPC)7: G06F 7/48, G06F 7/50, G06F 7/52
(86) International application number:
PCT/US0110/603
(87) International publication number:
WO 0107/5587 (11.10.2001 Gazette 2001/41)
(84) Designated Contracting States:
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
Designated Extension States:
AL LT LV MK RO SI

(30) Priority: 31.03.2000 US 539922

(71) Applicants:
  • INTEL CORPORATION
    Santa Clara, CA 95052 (US)
  • Analog Devices, Inc.
    Norwood,Massachusetts 02062-9106 (US)

(72) Inventors:
  • KOLAGOTLA, Ravi
    Austin, TX 78759 (US)
  • ALDRICH, Bradley, C.
    Austin, TX 78735 (US)
  • ANDERSON, William, C.
    Austin, TX 78731 (US)

(74) Representative: Loveless, Ian Mark 
Reddie & Grose,16 Theobalds Road
London WC1X 8PL
London WC1X 8PL (GB)

   


(54) MULTIPLIER ARCHITECTURE IN A GENERAL PURPOSE PROCESSOR OPTIMIZED FOR EFFICIENT MULTI-INPUT ADDITION