(19)
(11) EP 1 280 204 A8

(12) CORRECTED EUROPEAN PATENT APPLICATION

(48) Corrigendum issued on:
02.04.2003 Bulletin 2003/14

(43) Date of publication:
29.01.2003 Bulletin 2003/05

(21) Application number: 02013997.8

(22) Date of filing: 26.06.2002
(51) International Patent Classification (IPC)7: H01L 23/544
(84) Designated Contracting States:
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
Designated Extension States:
AL LT LV MK RO SI

(30) Priority: 27.06.2001 JP 2001194760

(71) Applicant: SHINKO ELECTRIC INDUSTRIES CO. LTD.
Nagano-shi, Nagano 380-0921 (JP)

(72) Inventors:
  • Sato, Yukio, c/o Shinko Electric Ind. Co. Ltd.
    Oaza Kurita, Nagano-shi, Nagano 380-0921 (JP)
  • Oku, Akihiro, Shinko Electric Ind. Co., Ltd.
    Oaza Kurita, Nagano-shi, Nagano 380-0921 (JP)
  • Aoki, Masayoshi, c/o Shinko Electr. Ind. Co. Ltd.
    Oaza Kurita, Nagano-shi, Nagano 380-0921 (JP)

(74) Representative: Schmidt, Steffen J., Dipl.-Ing. 
Wuesthoff & Wuesthoff, Patent- und Rechtsanwälte, Schweigerstrasse 2
81541 München
81541 München (DE)

   


(54) Wiring substrate having position information


(57) A wiring board for a semiconductor package comprises a base substrate having first and second surfaces; a wiring layer consisting of necessary wiring patterns formed on at least one of the first and second surfaces; a plurality of semiconductor element mounting areas formed on the surface of the base substrate on which the wiring layer is formed; and individual patterns as position information provided for the respective semiconductor element mounting areas, the individual patterns having a particular shape for the respective semiconductor element mounting area. The individual patterns as position information are formed on peripheral regions of the respective semiconductor element mounting areas.