Method for erasing a memory cell

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EP 1 306 855 A8

(12)	CORRECTED EUROPEAN PATENT APPLICATION

(48)	Corrigendum issued on:
	17.09.2003 Bulletin 2003/38

(43)	Date of publication:
	02.05.2003 Bulletin 2003/18

(21)	Application number: 02257381.0

(22)	Date of filing: 24.10.2002

(51)	International Patent Classification (IPC)⁷: G11C 16/14

(84)	Designated Contracting States:
	AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SK TR
	Designated Extension States:
	AL LT LV MK RO SI

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Priority:

24.10.2001 US 983510

(71)	Applicant: Saifun Semiconductors Ltd.
	Netanya 42505 (IL)

(72)	Inventors:
	Sofer, Yair Tel-Aviv 62265 (IL) Eitan, Boaz Ra'anana 43259 (IL)

(74)	Representative: Martin, Philip John
	Marks & Clerk, Cambridge Office, Wellington House East Road Cambridge CB1 1BH Cambridge CB1 1BH (GB)

(54)	Method for erasing a memory cell

(57) A method for erasing a non-volatile memory cell array, the method including applying an erase pulse to at least one bit of at least one memory cell of the array, erase verifying the at least one bit with a first erase verify level, and if the bit has passed the first erase verify level, applying at least one more erase pulse to the at least one bit.