METHOD FOR DESIGN AND LAYOUT OF INTEGRATED CIRCUITS - Patent 1307835

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(11)

EP 1 307 835 A2

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(88)	Date of publication A3:
	27.02.2003

(43)	Date of publication:
	07.05.2003 Bulletin 2003/19

(21)	Application number: 01952407.3

(22)	Date of filing: 02.07.2001

(51)	International Patent Classification (IPC)⁷: G06F 17/50

(86)	International application number:
	PCT/US0121/162

(87)	International publication number:
	WO 0200/3266 (10.01.2002 Gazette 2002/02)

(84)	Designated Contracting States:
	AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

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Priority:

30.06.2000 US 608542

(71)	Applicant: Infineon Technologies North America Corp.
	San Jose, CA 95112-4508 (US)

(72)	Inventor:
	FRANKOWSKY, Gerd 85635 Hohenkirchen-Siegertsbrunn (DE)

(74)	Representative: Epping Hermann & Fischer
	Ridlerstrasse 55 80339 München 80339 München (DE)

(54)	METHOD FOR DESIGN AND LAYOUT OF INTEGRATED CIRCUITS