(19)
(11) EP 1 326 475 A8

(12) CORRECTED EUROPEAN PATENT APPLICATION

(48) Corrigendum issued on:
12.11.2003 Bulletin 2003/46

(43) Date of publication:
09.07.2003 Bulletin 2003/28

(21) Application number: 02258237.3

(22) Date of filing: 29.11.2002
(51) International Patent Classification (IPC)7: H04Q 11/04, H04L 29/06
(84) Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SK TR
Designated Extension States:
AL LT LV MK RO SI

(30) Priority: 21.12.2001 US 29679

(71) Applicant: Agere Systems Inc.
Allentown, PA 18109 (US)

(72) Inventors:
  • Bouchard, Gregg A.
    Round Rock, Texas 78681 (US)
  • Calle, Mauricio
    Austin, Texas 78750 (US)
  • Davidson, Joel R.
    Austin, Texas 78727 (US)
  • Hathaway, Michael W.
    Austin, Texas 78746 (US)
  • Kirk, James T.
    Austin, Texas 78759 (US)
  • Walton, Christopher Brian
    Austin, Texas 78759 (US)

(74) Representative: Williams, David John et al
Page White & Farrer, 54 Doughty Street
London WC1N 2LS
London WC1N 2LS (GB)

   


(54) Method and apparatus using multiple packet reassembler and memories for performing multiple functions


(57) A packet processing system comprises first processing circuitry for performing a first function, and first memory circuitry coupled to the first processing circuitry for storing received packets, wherein at least a portion of the packets stored by the first memory circuitry are usable by the first processing circuitry in accordance with the first function. The packet processing system further comprises at least second processing circuitry for performing a second function, and at least second memory circuitry coupled to the second processing circuitry for storing at least a portion of the same packets stored in the first memory circuitry, wherein at least a portion of the packets stored in the second memory circuitry are usable by the second processing circuitry in accordance with the second function. In an illustrative embodiment, the first processing circuitry and the second processing circuitry operate in a packet switching device such as a router. In such case, the first processing circuitry and the second processing circuitry operate between a packet network interface and a switch fabric of the packet switching device.