Semiconductor devices, circuits and mehtods for synchronizing the inputting and outputting data by internal clock signals derived from single feedback loop

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EP 1 341 181 A8

(12)	CORRECTED EUROPEAN PATENT APPLICATION

(48)	Corrigendum issued on:
	07.01.2004 Bulletin 2004/02

(43)	Date of publication:
	03.09.2003 Bulletin 2003/36

(21)	Application number: 03250132.2

(22)	Date of filing: 09.01.2003

(51)	International Patent Classification (IPC)⁷: G11C 7/10

(84)	Designated Contracting States:
	AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT SE SI SK TR
	Designated Extension States:
	AL LT LV MK RO

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Priority:

09.01.2002 KR 2002001251

(71)	Applicant: SAMSUNG ELECTRONICS Co. Ltd.
	Kyungki-do, Seoul (KR)

(72)	Inventors:
	Jun, Young-Hyun Kangnam-ku., Seoul (KR) Kim, Chul-Soo Paldal-ku, Suwon, Kyunggi-do (KR) Song, Ho-Young Kiheung-eub., Yongin-si, Kyunggi-do (KR)

(74)	Representative: Mounteney, Simon James
	MARKS & CLERK, 57-60 Lincoln's Inn Fields London WC2A 3LS London WC2A 3LS (GB)

(54)	Semiconductor devices, circuits and mehtods for synchronizing the inputting and outputting data by internal clock signals derived from single feedback loop

(57) Devices, circuits and methods synchronize the inputting and outputting of groups of data into a memory cell array and out of a device. Synchronizing is performed by internal clock signals, both of which are derived from a single delay feedback loop.