RECESSED GATE DRAM TRANSISTOR AND METHOD - Patent 1382059

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EP 1 382 059 A2

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(88)	Date of publication A3:
	06.11.2003

(43)	Date of publication:
	21.01.2004 Bulletin 2004/04

(21)	Application number: 02731519.1

(22)	Date of filing: 26.04.2002

(51)	International Patent Classification (IPC)⁷: H01L 21/00

(86)	International application number:
	PCT/US2002/013196

(87)	International publication number:
	WO 2002/089182 (07.11.2002 Gazette 2002/45)

(84)	Designated Contracting States:
	AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
	Designated Extension States:
	AL LT LV MK RO SI

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Priority:

27.04.2001 US 842788

(71)	Applicant: MICRON TECHNOLOGY, INC.
	Boise, ID 83707-0006 (US)

(72)	Inventors:
	DURCAN, Mark, D. Boise, ID 83706 (US) LEE, Roger Boise, ID 83616 (US)

(74)	Representative: Collins, John David
	Marks & Clerk,57-60 Lincoln's Inn Fields London WC2A 3LS London WC2A 3LS (GB)

(54)	RECESSED GATE DRAM TRANSISTOR AND METHOD