High speed interface for radio systems

Abstract

 The present invention relates to a high speed interface for radio systems, in particular to a synchronous serial digital interface for car radio.
In an its embodiment the synchronous serial digital interface for at least dual radio receiver systems comprises a master device and a slave device; said dual radio receiver systems having an intermediate frequency; said master device and said slave device exchange data in bi-directional way on at least one communication channel; said master device and said slave device have a unique bit clock; said master device supply to said slave device a synchronisation signal; said synchronisation signal have frequency spectrum with an amplitude at said intermediate frequency lower than at the other frequencies.

Description

[0001] The present invention relates to a high speed interface for radio systems, in particular to a synchronous serial digital interface for car radio.

[0002] In radio applications the electro magnetic interference is a very important issue.

[0003] Further, in new systems on chip is required very high scale integration, in a smaller and smaller area, embedding many functions on CMOS technology. In order to cover a wide range of different customer requirements, and keep at the same time a low number of dedicated chip, device modular approach is a key point for market offer.

[0004] Moreover, a radio system has to deal with tiny analogue signal coming from antennas and turner front-ends.

[0005] Literature shows a huge variety of digital interfaces, which should reduce as much as possible electro magnetic emission. Further, none of them are specifically dedicated to dual or multi tuner radio receiver, where switching noise gives very significant contribution to performance degradation.

[0006] In view of the state of the art described, it is an obj ect of the present invention to provide a high speed interface for radio systems and in particular for car radio systems.

[0007] According to the present invention, such object is achieved by a synchronous serial digital interface for at least dual radio receiver systems comprising a master device and a slave device; said dual radio receiver systems having an intermediate frequency; said master device and said slave device exchange data in bi-directional way on at least one communication channel; said master device and said slave device have a unique bit clock; said master device supply to said slave device a synchronisation signal; said synchronisation signal have frequency spectrum with an amplitude at said intermediate frequency lower than at the other frequencies.

[0008] Furthermore according to the present invention, such object is achieved by an antenna diversity system for radio systems comprising a synchronous serial digital interface according to claim 1.

[0009] Thanks to the present invention is possible to have an interface that copes with systems where low emission, high speed, and high data transfer efficiency live together. The characteristic of the present interface give very low electro magnetic emission, thus leading to a very quiet interface, which can be freely integrated without bothering about noise when high rate data transfer operates.

[0010] The features and the advantages of the present invention will be made more evident by the following detailed description of a particular embodiment, illustrated as a non-limiting example in the annexed drawings, wherein:

Figure 1 shows a block scheme of a dual radio receiver system according to the present invention;

Figure 2 shows the timing diagram of the transfer data;

Figure 3 shows chip comprising an interface according to the present invention.

[0011] The dual radio receiver system shown in figure 1, include two antennas 10 and 11 connected respectively to two turner front end 12 and 13, which from antennas 10 and 11 takes the RF (radio frequency) and convert it to IF (intermediate frequency) of 10.7MHz.

[0012] The IF signals, coming from the turner front end 12 and 13 are supplied respectively to two digital signal processors (DSP) 14 and 15.

[0013] The digital signal processors 14 and 15 communicate between them by means of two synchronous serial digital interfaces 16 and 17 (respectively), according to present invention. The digital interface 16 is to be considered as a master and the digital interface 17 is to be considered as a slave. They use a single clock signal generated by the same crystal quartz 18. The master digital interface 16 supply to the slave digital interface 17 a synchronisation signal 19, and the digital interfaces 16 and 17 exchange their data in bi-directional way by means of the signals 20. The whole system has only one audio output 21.

[0014] To enhance the quality of FM stations, tuner diversity can be adopted, giving an impressive improvement to the reception even in adverse environments, where multi-path and fading effects are dominants, as well as suppressing strong adjacent channels.

[0015] According to the present invention two sets of turner front end 12 and 13 and digital signal processors 14 and 15 are connected together, to implement an antenna diversity system.

[0016] Signals coming from separate antennas are processed in each device, and then are exchanged between them by means of the digital interfaces 16 and 17. In this case with a proper algorithm is possible enhances quality of reception. The converted IF signals are gathered into the Master device which first analyse field strength of each of them: the one with insufficient field strength is dropped, and the other chosen; else, if both have significant strength, a proper amplitude and phase correction is performed before sum them up. That leads to an antennas beam forming, which is typically used in Radio Base Band Stations.

[0017] On the other hand the data exchange is at very high rate, very close to IF and FM bandwidth, hence the request to reduce as much as possible radiation from the digital interfaces 16 and 17 is raised. The digital interfaces 16 and 17 do not exchange a high speed clock, but only a synchronisation signal 19 is used to permits data rebuild in the slave interface.

[0018] The data rate is, in the present case, 1/256 the crystal frequency, i.e. 74.1 MHz/256 = 289.45kHz. Word length is 16bits, and 2 words are transmitted and/or received at a time, which leads to a bit rate for each channel of 289.45kHz*16*2 = 9.2625Mbit/sec. The synchronisation signal synchronises the digital interfaces 16 and 17 on its rising edge. Whereas in slave mode the synchronisation signal is received and extracted to internally initialise the blocks and send synchronously back the slave data stream.

[0019] Master interface 16 does not need send bit clock to slave, since both interfaces run off same crystal so instantly they are at the exactly same frequency, and slave only needs to recover the proper phase, to latch data in. The same clock phase is used by the slave to send out its own data.

[0020] Referring now to figure 2, the master interface 16 sends data Mi with a bit clock Ck running at 9.2625MHz, and a synchronisation signal MSynch with a rising edge (the synchronisation will be on the slave chip upon the rising edge of it) at the synchronisation rate Fs or period T₀. At the rising edge of the synchronisation signal start the transmission of data from the master interface 16 toward the slave interface 17.

[0021] The duty cycle D = τ/T₀ of the synchronisation signal MSynch can be adjusted among different values, at which the interference around the IF frequency (10.7MHz) is minimised.

[0022] The slave interface 17 is such that the master interface 16 can capture the slave Si bit at the rising edge of the master bit clock Ck just after the one which has previously generated the master Mi bit.

[0023] Data line has the maximum frequency of 9.26 MHz/2 = 4.63 MHz, when transmitting or receiving a sequence of 101010..., in general it can be assumed data sequence being random, thus spreading its frequency spectrum over the band.

[0024] The synchronisation signal gives the start of the frame, and the serial interface uses one on its edges to extract the synchronisation and to recover from serial to parallel format the data upon reception. One choice of the synchronisation signal is a square wave with a duty cycle D = τ/T₀, where T₀ is the period and τ is the time where the synchronisation signal is on.

[0025] The Fourier series expansion of a generic periodic function with period T₀ is:

   where

[0026] So in our analysis where F(t) is a square wave with duty cycle D = τ/T₀ we have:

[0027] Being T₀ = 1/289.45 KHz, the 37^th harmonics, that is 289.45 KHz*37 = 10.7095 MHz, falls inside the IF bandwidth (10.7 MHz). So, the 37^th coefficient of the Fourier series must be 0 or close to it, which leads to sin(πnD) = 0 or 37*π*D = k* π, or 37*D = k where k is any whole number. Hence we have to choose D = k/37. Being our time resolution 1/74.1 MHz we have D = δ/256, with δ any integer number within the range 0< δ<256. The best we can have is δ = 83, which leads A₃₇/A₀ = 2 sin (37*π*83/256)/(37*π), that is about -73 dB. Therefore, a preferable value for τ is τ = D*T₀ = δ/256 *T₀ = (83/256)*(1/289.45 KHz).

[0028] Of course other values can be found which can still give good rejection at the disturbing harmonic, for example value of D comprised between D = 75/256 and D = 90/256.

[0029] The rejection can be easily further reduced by increasing T₀ by a multiple M of it, for example 10 times, so that we have to consider the 37*M harmonic.

[0030] Alternatively, for a even better spreading of noise coming from harmonics of synchronisation signal, the duty cycle can be changed on the fly with a pseudo-random numeric sequence, thus giving more reduction to in-band interference. This can be easily performed by varying the value of δ from 1 to 127: a counter from 0 to 255 and a comparator with variable threshold originated of the sincronization signal; by varying the threshold with a pseudo random sequence of numbers from 1 to 127, for example stored in a look-up table, the duty cycle δ/D is modulated, and harmonics peak level reduced, thus whitening the noise due to radiation.

[0031] Referring now to figure 3, the interface can be partitioned in two main modules: the synchronisation signal manager 30, and the channel management blocks 31, 32, 33. It also contains the control status register (not shown), responsible for the set-up configuration of synchronisation and channel blocks.

[0032] In this specification the channel management blocks 31, 32, 33 are three, but can be any number, i.e. many blocks of the same kind can be placed more than once, provided the control status register contains enough bits for proper set-up configuration and data.

[0033] There are 2 main configurations of the interface, mutually exclusive.

[0034] The master one: in this case the interface is responsible for synchronisation signal generation MSynch, and gives the proper duty cycle shaping.

[0035] The slave one: in this case the interface is responsible for recovery of the synchronisation from the reception of master synchronisation signal MSynch, and it also synchronises all the channel blocks of the slave. It can also be used for the slave interface synchronisation.

[0036] When in master mode a down-up counter counting from 0 to 255 by 1 step and clocked at 74.1MHz provides the basic waveform for the MSynch signal to be output as master to the slave. It is then shaped with an offset, selectable from external by a register in the range 1 to 127, of which resulting MSB is the Msynch (as aforesaid); the duty cycle is D=offset/256. The offset should be set as described above. Internally the data are handled in parallel, thus a parallel to serial in transmit mode, and serial to parallel in receive mode conversions are needed. The 8bit counter overflow is the load signal for the parallel to serial or serial to parallel conversion in the channel management block, which performs the conversion, and send/receive data to/from the electrical interface.

[0037] When in slave mode the clock divide by 8 samples the incoming MSynch (from external master) with four 90degrees off phase clocks at 9.26MHz frequency. It defines the window, where the MSynch has its rising edge. The clock phase selector selects one out of the four phases (clk0, clk90, clk180, clk270), to be used as slave clock in the channel managers (PhasedClk). It also provides a synchronisation pulse at 74.1MHz to synchronise the 8bit counter, and in turn the load operation, as well as a slave synchronisation to be used elsewhere in the slave interface (for instance to resynchronise the slave interface to the master one). The interface also has a reset from outside and needs a 74.1MHz system clock. A start signal is also available to synchronisation the interface when in master mode.

[0038] The synchronisation signal manager 30 has the one shot feature which enables the MSynch out just once in a 32bit data frame upon request. This is to have the quietest environment possible, where the synchronisation between the two interfaces is done just once for example at the very beginning, or upon request by software.

[0039] Here the serial in/out data are handled, together with the parallel to serial and serial to parallel interface. The write and read operation to data registers can be done either from digital signal processors or to/from an hardware block, hooked up to it.

[0040] Even in channel management block there are two main configurations of the channel.

[0041] The transmitter one: parallel data are read from digital signal processors or other block, and properly loaded into the 32bit register to be sent out serially at 9.26MHz rate.

[0042] The receiver one: the 32bit register serially reads in data from master, with proper re-phased 9.26MHz, then transferred to the digital signal processors register for parallel read from outside

[0043] The 32bit register is essentially a mono directional 32 bit shift register, which can be up-loaded either from parallel bus (from DSP registers for instance) or from serial line (DataIn in our case), hooked up to the first bit, or can download its contents to parallel registers or to the serial out line (DataOut).

[0044] The signals of the interface, according to the present invention, are the followings.

[0045] Inputs.

• Clock: system clock at 74.1MHz.
• Resetn: main reset of all the sequential circuitry. Active Low.
• Start: for resynchronisation of all counters and internal synchronisation signals.
• MSynch: in Slave mode, synchronisation signal from external Master interface.
• HW0_0, _1, _2: data input to last 16bit of sent/received serial data of respectively Channel Management Blocks 0, 1, 2.
• HW1_0, _1, _2: data input to first 16bit of sent/received serial data of respectively Channel Management Blocks 0, 1, 2.
• DataIn0, 1, 2: serial data in receiver mode.
  Outputs.
• PhasedClk: phased clock output, to be used externally as signal (e.g. test purposes).
• Slave Synch: 1 pulse at 74.1MHz frequency, to be used as external synchronisation in Slave mode.
• Master Synch: synchronisation output signal when in master mode, with duty cycle controllable.
• SynchPadEnCtrl: controls direction of the synchronisation output. High impedance when in slave mode, output when in master mode.
• DataOut0, 1,2: serial data out in transmitter mode.
• PadEnCtr10, 1, 2: gives direction to the InOut serial data pad, High impedance when in receiver mode, output when in transmitter mode.
  Registers.
• DSPIF: data address interface (in/out) to the DSP core, for communication to it.
• Master/Slave Selection: bit which selects between Master (High) and Slave (Low). At reset it is Low (Slave).
• Offset: 7 bit value, which gives the offset for Master Synch output duty cycle. At reset equals 0.
• OneShot: when enabled, and in Master Mode the Master Synch is applied once in a data frame.
• TxRx0, 1, 2: for each block 1 bit select for transmitter (High), receiver (Low) mode. At reset is Low (Receiver).
• HwSwMode0, 1, 2: for each block 1 bit select for up/download from to either DSP (Low) or Hw block (High). At reset it is Low (DSP).

[0046] Preferably, the interface according to the present invention, as disclosed in figure 3, is carried out in a single chip.

[0047] The number of channels can be extended, since each channel management block is fully independent of each other. In a dual antenna diversity systems, the typical configuration is with master having two receiving channels (generally IF in phase and quadrature signals), and one transmitting channel, which is used for instructing the slave device.

Claims

1. Synchronous serial digital interface for at least dual radio receiver systems comprising a master device and a slave device;
   said dual radio receiver systems having an intermediate frequency;
   said master device and said slave device exchange data in bi-directional way on at least one communication channel;
   said master device and said slave device have a unique bit clock;
   said master device supply to said slave device a synchronisation signal;
   said synchronisation signal have frequency spectrum with an amplitude at said intermediate frequency lower than at the other frequencies.

2. Synchronous serial digital interface according to claim 1 characterized in that said synchronisation signal have a duty cycle comprised between D = 75/256 and D = 90/256.

3. Synchronous serial digital interface according to claim 1 characterized in that said synchronisation signal have a duty cycle variable according to a pseudo-random numeric sequence.

4. Synchronous serial digital interface according to claim 1 characterized in that said slave device do not supply to said master device a synchronisation signal.

5. Synchronous serial digital interface according to claim 1 characterized in that said master device receive the slave bit at the rising edge of the bit clock just after the one which has previously generated the master bit.

6. Synchronous serial digital interface according to claim 1 characterized in that at the rising edge of said synchronisation signal start the transmission of data from said master device to said slave device.

7. Antenna diversity system for radio systems comprising a synchronous serial digital interface according to claim 1.

Drawing