(19)
(11) EP 1 429 392 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
02.09.2009 Bulletin 2009/36

(43) Date of publication A2:
16.06.2004 Bulletin 2004/25

(21) Application number: 03027344.5

(22) Date of filing: 26.11.2003
(51) International Patent Classification (IPC): 
H01L 29/78(2006.01)
H01L 21/04(2006.01)
 H01L 29/24(2006.01)
(84) Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR
Designated Extension States:
AL LT LV MK

(30) Priority: 29.11.2002 JP 2002347183

(71) Applicant: Panasonic Corporation
Kadoma-shi Osaka 571-8501 (JP)

(72) Inventors:
  • Takahashi, Kunimasa
    Ibaraki-shi Osaka 567-0845 (JP)
  • Kusumoto, Osamu
    Nara-shi Nara 631-0013 (JP)
  • Kitabatake, Makoto
    Nara-shi Nara 631-0076 (JP)
  • Uchida, Masao
    Ibaraki-shi Osaka 567-0823 (JP)
  • Yamashita, Kenya
    Kadoma-shi Osaka 571-0074 (JP)

(74) Representative: Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät 
Leopoldstrasse 4
80802 München
80802 München (DE)

   


(54) SiC-misfet and method for fabricating the same


(57) A storage-type (accumulation-type) SiC-MISFET includes a SiC substrate, an n-type drift layer, a p-type well region, an n-type source region, a SiC channel layer which contains an n-type impurity and is a storage-type (accumulation-type) channel layer, a p-type heavily doped contact layer to contact the well layer, a gate insulation film, a gate electrode. The storage-type SiC-MISFET is characterized by a heavily doped layer formed by implanting ions of a p-conductivity type into an upper surface portion of the n-type drift layer at a higher concentration than that in the well region, before the formation of the channel layer. The planar gate SiC-MISFET can be of the vertical or of the horizontal type.







Search report