SYSTEMATIC OPTIMISATION OF INDIVIDUAL BLOCKS IN HIGH-SPEED CMOS CIRCUITS - Patent 1449301

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EP 1 449 301 A1

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(43)	Date of publication:
	25.08.2004 Bulletin 2004/35

(21)	Application number: 02746801.6

(22)	Date of filing: 26.06.2002

(51)	International Patent Classification (IPC)⁷: H03K 19/00

(86)	International application number:
	PCT/US2002/020872

(87)	International publication number:
	WO 2003/023965 (20.03.2003 Gazette 2003/12)

(84)	Designated Contracting States:
	AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
	Designated Extension States:
	AL LT LV MK RO SI

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Priority:

05.09.2001 US 947643
02.05.2002 US 137988

(71)	Applicant: Qantec Communications, Inc.
	Cupertino, CA 95014 (US)

(72)	Inventors:
	TUNG, John, C. Cupertino, CA 95014 (US) ZHANG, Minghao, (Mary) Cupertino, CA 95014 (US)

(74)	Representative: Perkins, Sarah
	Stevens, Hewlett & PerkinsHalton House20/23 Holborn London EC1N 2JD London EC1N 2JD (GB)

(54)	SYSTEMATIC OPTIMISATION OF INDIVIDUAL BLOCKS IN HIGH-SPEED CMOS CIRCUITS