(19)
(11) EP 1 524 594 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
12.04.2006 Bulletin 2006/15

(43) Date of publication A2:
20.04.2005 Bulletin 2005/16

(21) Application number: 04018745.2

(22) Date of filing: 06.08.2004
(51) International Patent Classification (IPC): 
G06F 7/72(2006.01)
(84) Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR
Designated Extension States:
AL HR LT LV MK

(30) Priority: 15.10.2003 US 686316

(71) Applicant: MICROSOFT CORPORATION
Redmond, WA 98052 (US)

(72) Inventor:
  • Montgomery, Peter L.
    Redmond Washington 98052 (US)

(74) Representative: Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät 
Maximilianstrasse 58
80538 München
80538 München (DE)

   


(54) Utilizing SIMD instructions within Montgomery multiplication


(57) Contemporary computer architectures support pipelining and instruction-level parallelism, in which an operation related to updating array T1 is followed by an operation related to updating array T2. To further improve performance, it is desirable to update arrays T1 and T2 together within the loop over i, using one instruction per pair of updates.
The computer architecture employs SIMD instructions (and in our particular example, SSE2 instructions) to update simultaneously the arrays T1 and T2 used in Montgomery multiplication, montmul (A,B).
This process involves, in part, processing digits of A in a right-to-left manner and interleaving results of the multiplications involving B (i.e., mul1*B[i]) and modulus N (i.e., mul2*N[i]) that are used to update arrays T1 and T2.







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