LOAD LOCK OPTIMIZATION METHOD AND SYSTEM - Patent 1540558

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EP 1 540 558 A2

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(88)	Date of publication A3:
	27.01.2005

(43)	Date of publication:
	15.06.2005 Bulletin 2005/24

(21)	Application number: 03752140.8

(22)	Date of filing: 10.09.2003

(51)	International Patent Classification (IPC)⁷: G06F 19/00

(86)	International application number:
	PCT/US2003/028213

(87)	International publication number:
	WO 2004/025701 (25.03.2004 Gazette 2004/13)

(84)	Designated Contracting States:
	AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR
	Designated Extension States:
	AL LT LV MK

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Priority:

10.09.2002 US 238305

(71)	Applicant: Varian Semiconductor Equipment Associates Inc.
	Gloucester, MA 01930 (US)

(72)	Inventor:
	EVANS, Morgan, D. Manchester, MA 01944 (US)

(74)	Representative: Boyce, Conor et al
	F.R. Kelly & Co,27 Clyde Road Ballsbridge,Dublin 4 Ballsbridge,Dublin 4 (IE)

(54)	LOAD LOCK OPTIMIZATION METHOD AND SYSTEM